/*
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* Copyright (C) 2013 The Android Open Source Project
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#include "trampoline_compiler.h"
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#include "base/arena_allocator.h"
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#include "base/malloc_arena_pool.h"
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#include "jni/jni_env_ext.h"
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#ifdef ART_ENABLE_CODEGEN_arm
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#include "utils/arm/assembler_arm_vixl.h"
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#endif
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#ifdef ART_ENABLE_CODEGEN_arm64
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#include "utils/arm64/assembler_arm64.h"
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#endif
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#ifdef ART_ENABLE_CODEGEN_mips
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#include "utils/mips/assembler_mips.h"
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#endif
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#ifdef ART_ENABLE_CODEGEN_mips64
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#include "utils/mips64/assembler_mips64.h"
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#endif
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#ifdef ART_ENABLE_CODEGEN_x86
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#include "utils/x86/assembler_x86.h"
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#endif
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#ifdef ART_ENABLE_CODEGEN_x86_64
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#include "utils/x86_64/assembler_x86_64.h"
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#endif
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#define __ assembler.
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namespace art {
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#ifdef ART_ENABLE_CODEGEN_arm
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namespace arm {
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#ifdef ___
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#error "ARM Assembler macro already defined."
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#else
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#define ___ assembler.GetVIXLAssembler()->
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#endif
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static std::unique_ptr<const std::vector<uint8_t>> CreateTrampoline(
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ArenaAllocator* allocator, EntryPointCallingConvention abi, ThreadOffset32 offset) {
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using vixl::aarch32::MemOperand;
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using vixl::aarch32::pc;
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using vixl::aarch32::r0;
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ArmVIXLAssembler assembler(allocator);
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switch (abi) {
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case kInterpreterAbi: // Thread* is first argument (R0) in interpreter ABI.
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___ Ldr(pc, MemOperand(r0, offset.Int32Value()));
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break;
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case kJniAbi: { // Load via Thread* held in JNIEnv* in first argument (R0).
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vixl::aarch32::UseScratchRegisterScope temps(assembler.GetVIXLAssembler());
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const vixl::aarch32::Register temp_reg = temps.Acquire();
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// VIXL will use the destination as a scratch register if
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// the offset is not encodable as an immediate operand.
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___ Ldr(temp_reg, MemOperand(r0, JNIEnvExt::SelfOffset(4).Int32Value()));
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___ Ldr(pc, MemOperand(temp_reg, offset.Int32Value()));
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break;
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}
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case kQuickAbi: // TR holds Thread*.
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___ Ldr(pc, MemOperand(tr, offset.Int32Value()));
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}
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__ FinalizeCode();
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size_t cs = __ CodeSize();
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std::unique_ptr<std::vector<uint8_t>> entry_stub(new std::vector<uint8_t>(cs));
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MemoryRegion code(entry_stub->data(), entry_stub->size());
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__ FinalizeInstructions(code);
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return std::move(entry_stub);
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}
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#undef ___
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} // namespace arm
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#endif // ART_ENABLE_CODEGEN_arm
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#ifdef ART_ENABLE_CODEGEN_arm64
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namespace arm64 {
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static std::unique_ptr<const std::vector<uint8_t>> CreateTrampoline(
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ArenaAllocator* allocator, EntryPointCallingConvention abi, ThreadOffset64 offset) {
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Arm64Assembler assembler(allocator);
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switch (abi) {
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case kInterpreterAbi: // Thread* is first argument (X0) in interpreter ABI.
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__ JumpTo(Arm64ManagedRegister::FromXRegister(X0), Offset(offset.Int32Value()),
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Arm64ManagedRegister::FromXRegister(IP1));
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break;
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case kJniAbi: // Load via Thread* held in JNIEnv* in first argument (X0).
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__ LoadRawPtr(Arm64ManagedRegister::FromXRegister(IP1),
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Arm64ManagedRegister::FromXRegister(X0),
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Offset(JNIEnvExt::SelfOffset(8).Int32Value()));
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__ JumpTo(Arm64ManagedRegister::FromXRegister(IP1), Offset(offset.Int32Value()),
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Arm64ManagedRegister::FromXRegister(IP0));
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break;
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case kQuickAbi: // X18 holds Thread*.
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__ JumpTo(Arm64ManagedRegister::FromXRegister(TR), Offset(offset.Int32Value()),
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Arm64ManagedRegister::FromXRegister(IP0));
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break;
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}
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__ FinalizeCode();
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size_t cs = __ CodeSize();
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std::unique_ptr<std::vector<uint8_t>> entry_stub(new std::vector<uint8_t>(cs));
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MemoryRegion code(entry_stub->data(), entry_stub->size());
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__ FinalizeInstructions(code);
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return std::move(entry_stub);
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}
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} // namespace arm64
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#endif // ART_ENABLE_CODEGEN_arm64
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#ifdef ART_ENABLE_CODEGEN_mips
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namespace mips {
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static std::unique_ptr<const std::vector<uint8_t>> CreateTrampoline(
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ArenaAllocator* allocator, EntryPointCallingConvention abi, ThreadOffset32 offset) {
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MipsAssembler assembler(allocator);
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switch (abi) {
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case kInterpreterAbi: // Thread* is first argument (A0) in interpreter ABI.
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__ LoadFromOffset(kLoadWord, T9, A0, offset.Int32Value());
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break;
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case kJniAbi: // Load via Thread* held in JNIEnv* in first argument (A0).
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__ LoadFromOffset(kLoadWord, T9, A0, JNIEnvExt::SelfOffset(4).Int32Value());
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__ LoadFromOffset(kLoadWord, T9, T9, offset.Int32Value());
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break;
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case kQuickAbi: // S1 holds Thread*.
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__ LoadFromOffset(kLoadWord, T9, S1, offset.Int32Value());
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}
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__ Jr(T9);
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__ NopIfNoReordering();
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__ Break();
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__ FinalizeCode();
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size_t cs = __ CodeSize();
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std::unique_ptr<std::vector<uint8_t>> entry_stub(new std::vector<uint8_t>(cs));
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MemoryRegion code(entry_stub->data(), entry_stub->size());
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__ FinalizeInstructions(code);
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return std::move(entry_stub);
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}
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} // namespace mips
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#endif // ART_ENABLE_CODEGEN_mips
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#ifdef ART_ENABLE_CODEGEN_mips64
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namespace mips64 {
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static std::unique_ptr<const std::vector<uint8_t>> CreateTrampoline(
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ArenaAllocator* allocator, EntryPointCallingConvention abi, ThreadOffset64 offset) {
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Mips64Assembler assembler(allocator);
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switch (abi) {
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case kInterpreterAbi: // Thread* is first argument (A0) in interpreter ABI.
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__ LoadFromOffset(kLoadDoubleword, T9, A0, offset.Int32Value());
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break;
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case kJniAbi: // Load via Thread* held in JNIEnv* in first argument (A0).
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__ LoadFromOffset(kLoadDoubleword, T9, A0, JNIEnvExt::SelfOffset(8).Int32Value());
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__ LoadFromOffset(kLoadDoubleword, T9, T9, offset.Int32Value());
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break;
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case kQuickAbi: // Fall-through.
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__ LoadFromOffset(kLoadDoubleword, T9, S1, offset.Int32Value());
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}
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__ Jr(T9);
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__ Nop();
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__ Break();
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__ FinalizeCode();
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size_t cs = __ CodeSize();
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std::unique_ptr<std::vector<uint8_t>> entry_stub(new std::vector<uint8_t>(cs));
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MemoryRegion code(entry_stub->data(), entry_stub->size());
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__ FinalizeInstructions(code);
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return std::move(entry_stub);
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}
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} // namespace mips64
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#endif // ART_ENABLE_CODEGEN_mips
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#ifdef ART_ENABLE_CODEGEN_x86
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namespace x86 {
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static std::unique_ptr<const std::vector<uint8_t>> CreateTrampoline(ArenaAllocator* allocator,
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ThreadOffset32 offset) {
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X86Assembler assembler(allocator);
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// All x86 trampolines call via the Thread* held in fs.
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__ fs()->jmp(Address::Absolute(offset));
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__ int3();
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__ FinalizeCode();
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size_t cs = __ CodeSize();
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std::unique_ptr<std::vector<uint8_t>> entry_stub(new std::vector<uint8_t>(cs));
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MemoryRegion code(entry_stub->data(), entry_stub->size());
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__ FinalizeInstructions(code);
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return std::move(entry_stub);
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}
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} // namespace x86
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#endif // ART_ENABLE_CODEGEN_x86
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#ifdef ART_ENABLE_CODEGEN_x86_64
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namespace x86_64 {
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static std::unique_ptr<const std::vector<uint8_t>> CreateTrampoline(ArenaAllocator* allocator,
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ThreadOffset64 offset) {
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x86_64::X86_64Assembler assembler(allocator);
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// All x86 trampolines call via the Thread* held in gs.
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__ gs()->jmp(x86_64::Address::Absolute(offset, true));
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__ int3();
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__ FinalizeCode();
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size_t cs = __ CodeSize();
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std::unique_ptr<std::vector<uint8_t>> entry_stub(new std::vector<uint8_t>(cs));
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MemoryRegion code(entry_stub->data(), entry_stub->size());
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__ FinalizeInstructions(code);
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return std::move(entry_stub);
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}
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} // namespace x86_64
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#endif // ART_ENABLE_CODEGEN_x86_64
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std::unique_ptr<const std::vector<uint8_t>> CreateTrampoline64(InstructionSet isa,
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EntryPointCallingConvention abi,
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ThreadOffset64 offset) {
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MallocArenaPool pool;
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ArenaAllocator allocator(&pool);
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switch (isa) {
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#ifdef ART_ENABLE_CODEGEN_arm64
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case InstructionSet::kArm64:
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return arm64::CreateTrampoline(&allocator, abi, offset);
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#endif
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#ifdef ART_ENABLE_CODEGEN_mips64
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case InstructionSet::kMips64:
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return mips64::CreateTrampoline(&allocator, abi, offset);
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#endif
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#ifdef ART_ENABLE_CODEGEN_x86_64
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case InstructionSet::kX86_64:
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return x86_64::CreateTrampoline(&allocator, offset);
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#endif
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default:
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UNUSED(abi);
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UNUSED(offset);
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LOG(FATAL) << "Unexpected InstructionSet: " << isa;
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UNREACHABLE();
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}
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}
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std::unique_ptr<const std::vector<uint8_t>> CreateTrampoline32(InstructionSet isa,
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EntryPointCallingConvention abi,
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ThreadOffset32 offset) {
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MallocArenaPool pool;
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ArenaAllocator allocator(&pool);
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switch (isa) {
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#ifdef ART_ENABLE_CODEGEN_arm
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case InstructionSet::kArm:
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case InstructionSet::kThumb2:
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return arm::CreateTrampoline(&allocator, abi, offset);
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#endif
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#ifdef ART_ENABLE_CODEGEN_mips
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case InstructionSet::kMips:
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return mips::CreateTrampoline(&allocator, abi, offset);
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#endif
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#ifdef ART_ENABLE_CODEGEN_x86
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case InstructionSet::kX86:
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UNUSED(abi);
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return x86::CreateTrampoline(&allocator, offset);
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#endif
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default:
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LOG(FATAL) << "Unexpected InstructionSet: " << isa;
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UNREACHABLE();
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}
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}
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} // namespace art
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