/*****************************************************************************
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* Copyright(c) 2007, RealTEK Technology Inc. All Right Reserved.
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*
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* Module: Hal819xUsbDM.h (RTL8192 Header H File)
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*
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*
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* Note: For dynamic control definition constant structure.
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*
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*
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* Export:
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*
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* Abbrev:
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*
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* History:
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* Data Who Remark
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* 10/04/2007 MHC Create initial version.
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*
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*****************************************************************************/
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/* Check to see if the file has been included already. */
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#ifndef __R8192UDM_H__
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#define __R8192UDM_H__
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/*--------------------------Define Parameters-------------------------------*/
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#define DM_DIG_THRESH_HIGH 40
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#define DM_DIG_THRESH_LOW 35
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#define DM_DIG_HIGH_PWR_THRESH_HIGH 75
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#define DM_DIG_HIGH_PWR_THRESH_LOW 70
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#define BW_AUTO_SWITCH_HIGH_LOW 25
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#define BW_AUTO_SWITCH_LOW_HIGH 30
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#define DM_check_fsync_time_interval 500
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#define DM_DIG_BACKOFF 12
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#define DM_DIG_MAX 0x36
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#define DM_DIG_MIN 0x1c
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#define DM_DIG_MIN_Netcore 0x12
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#define RxPathSelection_SS_TH_low 30
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#define RxPathSelection_diff_TH 18
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#define RateAdaptiveTH_High 50
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#define RateAdaptiveTH_Low_20M 30
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#define RateAdaptiveTH_Low_40M 10
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#define VeryLowRSSI 15
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#define CTSToSelfTHVal 30
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/* defined by vivi, for tx power track */
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#define E_FOR_TX_POWER_TRACK 300
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/* Dynamic Tx Power Control Threshold */
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#define TX_POWER_NEAR_FIELD_THRESH_HIGH 68
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#define TX_POWER_NEAR_FIELD_THRESH_LOW 62
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/* added by amy for atheros AP */
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#define TX_POWER_ATHEROAP_THRESH_HIGH 78
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#define TX_POWER_ATHEROAP_THRESH_LOW 72
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/* defined by vivi, for showing on UI */
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#define Current_Tx_Rate_Reg 0x1b8
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#define Initial_Tx_Rate_Reg 0x1b9
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#define Tx_Retry_Count_Reg 0x1ac
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#define RegC38_TH 20
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/*--------------------------Define Parameters-------------------------------*/
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/*------------------------------Define structure----------------------------*/
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/* 2007/10/04 MH Define upper and lower threshold of DIG enable or disable. */
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struct dig {
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u8 dig_enable_flag;
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u8 dig_algorithm;
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u8 dbg_mode;
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u8 dig_algorithm_switch;
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long rssi_low_thresh;
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long rssi_high_thresh;
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long rssi_high_power_lowthresh;
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long rssi_high_power_highthresh;
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u8 dig_state;
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u8 dig_highpwr_state;
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u8 cur_connect_state;
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u8 pre_connect_state;
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u8 curpd_thstate;
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u8 prepd_thstate;
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u8 curcs_ratio_state;
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u8 precs_ratio_state;
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u32 pre_ig_value;
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u32 cur_ig_value;
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u8 backoff_val;
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u8 rx_gain_range_max;
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u8 rx_gain_range_min;
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bool initialgain_lowerbound_state;
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long rssi_val;
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};
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typedef enum tag_dynamic_init_gain_state_definition {
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DM_STA_DIG_OFF = 0,
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DM_STA_DIG_ON,
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DM_STA_DIG_MAX
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} dm_dig_sta_e;
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/* 2007/10/08 MH Define RATR state. */
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typedef enum tag_dynamic_ratr_state_definition {
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DM_RATR_STA_HIGH = 0,
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DM_RATR_STA_MIDDLE = 1,
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DM_RATR_STA_LOW = 2,
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DM_RATR_STA_MAX
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} dm_ratr_sta_e;
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/* 2007/10/11 MH Define DIG operation type. */
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typedef enum tag_dynamic_init_gain_operation_type_definition {
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DIG_TYPE_THRESH_HIGH = 0,
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DIG_TYPE_THRESH_LOW = 1,
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DIG_TYPE_THRESH_HIGHPWR_HIGH = 2,
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DIG_TYPE_THRESH_HIGHPWR_LOW = 3,
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DIG_TYPE_DBG_MODE = 4,
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DIG_TYPE_RSSI = 5,
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DIG_TYPE_ALGORITHM = 6,
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DIG_TYPE_BACKOFF = 7,
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DIG_TYPE_PWDB_FACTOR = 8,
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DIG_TYPE_RX_GAIN_MIN = 9,
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DIG_TYPE_RX_GAIN_MAX = 10,
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DIG_TYPE_ENABLE = 20,
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DIG_TYPE_DISABLE = 30,
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DIG_OP_TYPE_MAX
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} dm_dig_op_e;
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typedef enum tag_dig_algorithm_definition {
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DIG_ALGO_BY_FALSE_ALARM = 0,
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DIG_ALGO_BY_RSSI = 1,
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DIG_ALGO_MAX
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} dm_dig_alg_e;
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typedef enum tag_dig_dbgmode_definition {
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DIG_DBG_OFF = 0,
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DIG_DBG_ON = 1,
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DIG_DBG_MAX
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} dm_dig_dbg_e;
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typedef enum tag_dig_connect_definition {
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DIG_DISCONNECT = 0,
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DIG_CONNECT = 1,
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DIG_CONNECT_MAX
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} dm_dig_connect_e;
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typedef enum tag_dig_packetdetection_threshold_definition {
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DIG_PD_AT_LOW_POWER = 0,
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DIG_PD_AT_NORMAL_POWER = 1,
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DIG_PD_AT_HIGH_POWER = 2,
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DIG_PD_MAX
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} dm_dig_pd_th_e;
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typedef enum tag_dig_cck_cs_ratio_state_definition {
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DIG_CS_RATIO_LOWER = 0,
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DIG_CS_RATIO_HIGHER = 1,
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DIG_CS_MAX
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} dm_dig_cs_ratio_e;
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struct dynamic_rx_path_sel {
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u8 Enable;
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u8 DbgMode;
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u8 cck_method;
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u8 cck_Rx_path;
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u8 SS_TH_low;
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u8 diff_TH;
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u8 disabledRF;
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u8 reserved;
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u8 rf_rssi[4];
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u8 rf_enable_rssi_th[4];
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long cck_pwdb_sta[4];
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};
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typedef enum tag_CCK_Rx_Path_Method_Definition {
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CCK_Rx_Version_1 = 0,
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CCK_Rx_Version_2 = 1,
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CCK_Rx_Version_MAX
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} DM_CCK_Rx_Path_Method;
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typedef enum tag_DM_DbgMode_Definition {
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DM_DBG_OFF = 0,
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DM_DBG_ON = 1,
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DM_DBG_MAX
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} DM_DBG_E;
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typedef struct tag_Tx_Config_Cmd_Format {
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u32 Op; /* Command packet type. */
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u32 Length; /* Command packet length. */
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u32 Value;
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} DCMD_TXCMD_T, *PDCMD_TXCMD_T;
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/*------------------------------Define structure----------------------------*/
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/*------------------------Export global variable----------------------------*/
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extern struct dig dm_digtable;
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extern u8 dm_shadow[16][256];
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extern struct dynamic_rx_path_sel DM_RxPathSelTable;
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/*------------------------Export global variable----------------------------*/
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/*------------------------Export Marco Definition---------------------------*/
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/*------------------------Export Marco Definition---------------------------*/
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/*--------------------------Exported Function prototype---------------------*/
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void init_hal_dm(struct net_device *dev);
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void deinit_hal_dm(struct net_device *dev);
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void hal_dm_watchdog(struct net_device *dev);
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void init_rate_adaptive(struct net_device *dev);
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void dm_txpower_trackingcallback(struct work_struct *work);
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void dm_restore_dynamic_mechanism_state(struct net_device *dev);
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void dm_backup_dynamic_mechanism_state(struct net_device *dev);
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void dm_change_dynamic_initgain_thresh(struct net_device *dev,
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u32 dm_type, u32 dm_value);
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void dm_force_tx_fw_info(struct net_device *dev,
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u32 force_type, u32 force_value);
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void dm_init_edca_turbo(struct net_device *dev);
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void dm_rf_operation_test_callback(unsigned long data);
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void dm_rf_pathcheck_workitemcallback(struct work_struct *work);
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void dm_fsync_timer_callback(unsigned long data);
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void dm_cck_txpower_adjust(struct net_device *dev, bool binch14);
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void dm_shadow_init(struct net_device *dev);
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void dm_initialize_txpower_tracking(struct net_device *dev);
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/*--------------------------Exported Function prototype---------------------*/
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#endif /*__R8192UDM_H__ */
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/* End of r8192U_dm.h */
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