/*
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* Allwinner SoCs display driver.
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*
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* Copyright (C) 2016 Allwinner.
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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/**
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* All Winner Tech, All Right Reserved. 2014-2015 Copyright (c)
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*
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* File name : de_vsu_type.h
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*
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* Description : display engine 2.0 vsu struct declaration
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*
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* History : 2014/03/20 vito cheng v0.1 Initial version
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*
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*/
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#ifndef __DE_VSU_TYPE_H__
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#define __DE_VSU_TYPE_H__
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/*
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* __vsu_reg_t
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*/
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union VSU_CTRL_REG {
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unsigned int dwval;
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struct {
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unsigned int en:1;
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unsigned int res0:3;
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unsigned int coef_switch_rdy:1;
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unsigned int res1:25;
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unsigned int reset:1;
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unsigned int bist:1;
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} bits;
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};
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union VSU_STATUS_REG {
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unsigned int dwval;
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struct {
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unsigned int res0:4;
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unsigned int busy:1;
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unsigned int res1:11;
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unsigned int line_cnt:12;
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unsigned int res2:4;
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} bits;
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};
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union VSU_FIELD_CTRL_REG {
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unsigned int dwval;
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struct {
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unsigned int vphase_sel_en:1;
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unsigned int res0:31;
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} bits;
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};
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union VSU_OUTSIZE_REG {
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unsigned int dwval;
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struct {
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unsigned int width:13;
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unsigned int res0:3;
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unsigned int height:13;
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unsigned int res1:3;
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} bits;
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};
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union VSU_INSIZE_REG {
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unsigned int dwval;
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struct {
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unsigned int width:13;
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unsigned int res0:3;
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unsigned int height:13;
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unsigned int res1:3;
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} bits;
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};
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union VSU_HSTEP_REG {
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unsigned int dwval;
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struct {
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unsigned int res0:1;
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unsigned int frac:19;
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unsigned int integer:4;
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unsigned int res1:8;
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} bits;
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};
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union VSU_VSTEP_REG {
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unsigned int dwval;
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struct {
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unsigned int res0:1;
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unsigned int frac:19;
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unsigned int integer:4;
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unsigned int res1:8;
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} bits;
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};
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union VSU_HPHASE_REG {
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unsigned int dwval;
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struct {
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unsigned int res0:1;
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unsigned int frac:19;
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unsigned int integer:4;
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unsigned int res1:8;
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} bits;
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};
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union VSU_VPHASE0_REG {
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unsigned int dwval;
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struct {
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unsigned int res0:1;
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unsigned int frac:19;
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unsigned int integer:4;
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unsigned int res1:8;
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} bits;
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};
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union VSU_VPHASE1_REG {
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unsigned int dwval;
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struct {
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unsigned int res0:1;
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unsigned int frac:19;
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unsigned int integer:4;
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unsigned int res1:8;
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} bits;
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};
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union VSU_COEFF_REG {
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unsigned int dwval;
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struct {
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unsigned int coef0:8;
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unsigned int coef1:8;
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unsigned int coef2:8;
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unsigned int coef3:8;
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} bits;
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};
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struct __vsu_reg_t {
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union VSU_CTRL_REG ctrl; /* 0x0000 */
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unsigned int res0; /* 0x0004 */
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union VSU_STATUS_REG status; /* 0x0008 */
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union VSU_FIELD_CTRL_REG field; /* 0x000c */
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unsigned int res1[12]; /* 0x0010-3c */
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union VSU_OUTSIZE_REG outsize; /* 0x0040 */
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unsigned int res13[15]; /* 0x0044-0x07c */
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union VSU_INSIZE_REG ysize; /* 0x0080 */
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unsigned int res2; /* 0x0084 */
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union VSU_HSTEP_REG yhstep; /* 0x0088 */
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union VSU_VSTEP_REG yvstep; /* 0x008C */
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union VSU_HPHASE_REG yhphase; /* 0x0090 */
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unsigned int res3; /* 0x0094 */
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union VSU_VPHASE0_REG yvphase0; /* 0x0098 */
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union VSU_VPHASE1_REG yvphase1; /* 0x009c */
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unsigned int res4[8]; /* 0x00a0-bc */
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union VSU_INSIZE_REG csize; /* 0x00c0 */
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unsigned int res5; /* 0x00c4 */
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union VSU_HSTEP_REG chstep; /* 0x00c8 */
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union VSU_VSTEP_REG cvstep; /* 0x00cC */
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union VSU_HPHASE_REG chphase; /* 0x00d0 */
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unsigned int res6; /* 0x00d4 */
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union VSU_VPHASE0_REG cvphase0; /* 0x00d8 */
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union VSU_VPHASE1_REG cvphase1; /* 0x00dc */
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unsigned int res7[72]; /* 0x00e0-0x1fc */
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union VSU_COEFF_REG yhcoeff0[32]; /* 0x0200-0x27c */
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unsigned int res8[32]; /* 0x0280-0x2fc */
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union VSU_COEFF_REG yhcoeff1[32]; /* 0x0300-0x37c */
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unsigned int res9[32]; /* 0x0380-0x3fc */
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union VSU_COEFF_REG yvcoeff[32]; /* 0x0400-0x47c */
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unsigned int res10[96]; /* 0x0480-0x5fc */
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union VSU_COEFF_REG chcoeff0[32]; /* 0x0600-0x67c */
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unsigned int res11[32]; /* 0x0680-0x6fc */
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union VSU_COEFF_REG chcoeff1[32]; /* 0x0700-0x77c */
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unsigned int res12[32]; /* 0x0780-0x7fc */
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union VSU_COEFF_REG cvcoeff[32]; /* 0x0800-0x87c */
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};
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#endif
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