/*
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* Allwinner SoCs display driver.
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*
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* Copyright (C) 2016 Allwinner.
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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/*******************************************************************************
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* All Winner Tech, All Right Reserved. 2014-2015 Copyright (c)
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*
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* File name : de_peak_type.h
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*
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* Description : display engine 2.0 peak struct declaration
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*
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* History : 2014/03/26 vito cheng v0.1 Initial version
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*
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******************************************************************************/
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#ifndef __DE_PEAK_TYPE_H__
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#define __DE_PEAK_TYPE_H__
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#include "de_rtmx.h"
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#define PEAK_PARA_NUM 3
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#define PEAK_MODE_NUM 3
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union LP_CTRL_REG {
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unsigned int dwval;
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struct {
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unsigned int en:1;
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unsigned int res0:7;
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unsigned int win_en:1;
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unsigned int res1:23;
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} bits;
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};
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union LP_SIZE_REG {
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unsigned int dwval;
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struct {
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unsigned int width:12;
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unsigned int res0:4;
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unsigned int height:12;
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unsigned int res1:4;
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} bits;
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};
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union LP_WIN0_REG {
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unsigned int dwval;
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struct {
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unsigned int win_left:12;
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unsigned int res0:4;
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unsigned int win_top:12;
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unsigned int res1:4;
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} bits;
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};
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union LP_WIN1_REG {
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unsigned int dwval;
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struct {
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unsigned int win_right:12;
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unsigned int res0:4;
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unsigned int win_bot:12;
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unsigned int res1:4;
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} bits;
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};
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union LP_FILTER_REG {
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unsigned int dwval;
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struct {
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unsigned int bp1_ratio:6;
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unsigned int res0:2;
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unsigned int bp0_ratio:6;
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unsigned int res1:2;
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unsigned int hp_ratio:6;
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unsigned int res2:9;
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unsigned int filter_sel:1;
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} bits;
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};
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union LP_CSTM_FILTER0_REG {
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unsigned int dwval;
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struct {
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unsigned int c0:9;
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unsigned int res0:7;
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unsigned int c1:9;
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unsigned int res1:7;
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} bits;
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};
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union LP_CSTM_FILTER1_REG {
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unsigned int dwval;
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struct {
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unsigned int c2:9;
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unsigned int res0:7;
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unsigned int c3:9;
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unsigned int res1:7;
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} bits;
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};
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union LP_CSTM_FILTER2_REG {
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unsigned int dwval;
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struct {
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unsigned int c4:9;
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unsigned int res0:23;
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} bits;
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};
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union LP_GAIN_REG {
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unsigned int dwval;
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struct {
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unsigned int gain:8;
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unsigned int res0:24;
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} bits;
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};
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union LP_GAINCTRL_REG {
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unsigned int dwval;
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struct {
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unsigned int beta:5;
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unsigned int res0:11;
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unsigned int dif_up:8;
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unsigned int res1:8;
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} bits;
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};
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union LP_SHOOTCTRL_REG {
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unsigned int dwval;
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struct {
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unsigned int neg_gain:6;
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unsigned int res0:26;
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} bits;
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};
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union LP_CORING_REG {
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unsigned int dwval;
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struct {
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unsigned int corthr:8;
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unsigned int res0:24;
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} bits;
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};
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struct __peak_reg_t {
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union LP_CTRL_REG ctrl; /* 0x0000 */
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union LP_SIZE_REG size; /* 0x0004 */
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union LP_WIN0_REG win0; /* 0x0008 */
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union LP_WIN1_REG win1; /* 0x000c */
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union LP_FILTER_REG filter; /* 0x0010 */
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union LP_CSTM_FILTER0_REG cfilter0; /* 0x0014 */
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union LP_CSTM_FILTER1_REG cfilter1; /* 0x0018 */
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union LP_CSTM_FILTER2_REG cfilter2; /* 0x001c */
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union LP_GAIN_REG gain; /* 0x0020 */
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union LP_GAINCTRL_REG gainctrl; /* 0x0024 */
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union LP_SHOOTCTRL_REG shootctrl; /* 0x0028 */
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union LP_CORING_REG coring; /* 0x002c */
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};
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struct __peak_config_data {
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/* peak */
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unsigned int peak_en;
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unsigned int gain;
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unsigned int hp_ratio;
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unsigned int bp0_ratio;
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/* window */
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unsigned int win_en;
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struct de_rect win;
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};
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#endif
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