/*
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* Allwinner SoCs display driver.
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*
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* Copyright (C) 2016 Allwinner.
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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/**
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* All Winner Tech, All Right Reserved. 2014-2015 Copyright (c)
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*
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* File name : de_gsu_type.h
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*
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* Description : display engine 2.0 gsu struct declaration
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*
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* History : 2014/03/20 vito cheng v0.1 Initial version
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*
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*/
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#ifndef __DE_GSU_TYPE_H__
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#define __DE_GSU_TYPE_H__
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/*
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* __gsu_reg_t
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*/
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union GSU_CTRL_REG {
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unsigned int dwval;
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struct {
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unsigned int en:1;
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unsigned int res0:3;
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unsigned int coef_switch_rdy:1;
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unsigned int res1:25;
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unsigned int reset:1;
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unsigned int res2:1;
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} bits;
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};
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union GSU_STATUS_REG {
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unsigned int dwval;
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struct {
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unsigned int res0:4;
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unsigned int busy:1;
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unsigned int res1:11;
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unsigned int line_cnt:12;
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unsigned int res2:4;
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} bits;
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};
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union GSU_FIELD_CTRL_REG {
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unsigned int dwval;
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struct {
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unsigned int vphase_sel_en:1;
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unsigned int res0:31;
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} bits;
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};
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union GSU_BIST_REG {
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unsigned int dwval;
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struct {
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unsigned int bist_en:1;
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unsigned int res0:15;
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unsigned int bist_sel:5;
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unsigned int res1:11;
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} bits;
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};
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union GSU_OUTSIZE_REG {
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unsigned int dwval;
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struct {
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unsigned int width:13;
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unsigned int res0:3;
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unsigned int height:13;
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unsigned int res1:3;
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} bits;
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};
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union GSU_INSIZE_REG {
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unsigned int dwval;
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struct {
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unsigned int width:13;
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unsigned int res0:3;
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unsigned int height:13;
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unsigned int res1:3;
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} bits;
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};
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union GSU_HSTEP_REG {
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unsigned int dwval;
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struct {
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unsigned int res0:2;
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unsigned int frac:18;
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unsigned int integer:5;
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unsigned int res1:7;
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} bits;
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};
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union GSU_VSTEP_REG {
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unsigned int dwval;
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struct {
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unsigned int res0:2;
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unsigned int frac:18;
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unsigned int integer:5;
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unsigned int res1:7;
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} bits;
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};
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union GSU_HPHASE_REG {
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unsigned int dwval;
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struct {
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unsigned int res0:2;
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unsigned int frac:18;
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unsigned int integer:5;
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unsigned int res1:7;
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} bits;
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};
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union GSU_VPHASE0_REG {
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unsigned int dwval;
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struct {
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unsigned int res0:2;
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unsigned int frac:18;
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unsigned int integer:5;
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unsigned int res1:7;
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} bits;
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};
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union GSU_VPHASE1_REG {
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unsigned int dwval;
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struct {
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unsigned int res0:2;
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unsigned int frac:18;
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unsigned int integer:4;
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unsigned int res1:8;
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} bits;
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};
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union GSU_HCOEFF_REG {
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unsigned int dwval;
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struct {
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unsigned int coef0:8;
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unsigned int coef1:8;
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unsigned int coef2:8;
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unsigned int coef3:8;
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} bits;
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};
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struct __gsu_reg_t {
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union GSU_CTRL_REG ctrl; /* 0x0000 */
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unsigned int res0; /* 0x0004 */
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union GSU_STATUS_REG status; /* 0x0008 */
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union GSU_FIELD_CTRL_REG field; /* 0x000c */
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union GSU_BIST_REG bist; /* 0x0010 */
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unsigned int res1[11]; /* 0x0014-3c */
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union GSU_OUTSIZE_REG outsize; /* 0x0040 */
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unsigned int res5[15]; /* 0x0044-0x07c */
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union GSU_INSIZE_REG insize; /* 0x0080 */
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unsigned int res2; /* 0x0084 */
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union GSU_HSTEP_REG hstep; /* 0x0088 */
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union GSU_VSTEP_REG vstep; /* 0x008C */
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union GSU_HPHASE_REG hphase; /* 0x0090 */
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unsigned int res3; /* 0x0094 */
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union GSU_VPHASE0_REG vphase0; /* 0x0098 */
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union GSU_VPHASE1_REG vphase1; /* 0x009c */
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unsigned int res4[88]; /* 0x00a0-1fc */
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union GSU_HCOEFF_REG hcoeff[16]; /* 0x0200-0x23c */
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};
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#endif
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