/*
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* drivers/devfreq/dramfreq/sunxi-mdfs.h
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*
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* Copyright(c) 2013-2015 Allwinnertech Co., Ltd.
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*
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* Author: Pan Nan <pannan@allwinnertech.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*/
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#ifndef __MDFS_H__
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#define __MDFS_H__
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#include <asm/memory.h>
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#include <asm/sizes.h>
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#include <asm/io.h>
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#ifdef CONFIG_ARCH_SUN9IW1P1
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#define SRAM_DDRFREQ_SIZE (SZ_16K)
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/* register define */
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#define MCTL_COM_BASE ((void *)(0xf1c62000))
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#define MCTL_CTL_BASE ((void *)(0xf1c63000))
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#define MCTL_PHY_BASE ((void *)(0xf1c65000))
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#define CCM_PLL_BASE ((void *)(0xf6000000))
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#define CCM_MOD_BASE ((void *)(0xf6000400))
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#define UART_BASE ((void *)(0xf7000000))
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#define R_PRCM_BASE ((void *)(0xf8001400))
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#define CNT64_CTRL_REG ((void *)(0xf8001c00))
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#define MC_CR (MCTL_COM_BASE + 0x00)
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#define MC_CCR (MCTL_COM_BASE + 0x04)
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#define MC_RMCR (MCTL_COM_BASE + 0x10)
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#define M0_STATR (MCTL_CTL_BASE + 0x004)
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#define M0_MRCTRL0 (MCTL_CTL_BASE + 0x010)
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#define M0_PWRCTL (MCTL_CTL_BASE + 0x030)
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#define M0_RFSHCTL3 (MCTL_CTL_BASE + 0x060)
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#define M0_RFSHTMG (MCTL_CTL_BASE + 0x064)
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#define M0_RANKCTL (MCTL_CTL_BASE + 0x0f4)
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#define M0_ODTMAP (MCTL_CTL_BASE + 0x244)
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#define M0_DCMDAPC (MCTL_CTL_BASE + 0x304)
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#define P0_PIR (MCTL_PHY_BASE + 0x004)
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#define P0_PGCR0 (MCTL_PHY_BASE + 0x008)
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#define P0_PGCR3 (MCTL_PHY_BASE + 0x014)
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#define P0_PGSR0 (MCTL_PHY_BASE + 0x018)
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#define P0_PLLGCR (MCTL_PHY_BASE + 0x020)
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#define P0_PTR1 (MCTL_PHY_BASE + 0x028)
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#define P0_MR1 (MCTL_PHY_BASE + 0x0a0)
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#define P0_DTCR (MCTL_PHY_BASE + 0x0B0)
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#define P0_DSGCR (MCTL_PHY_BASE + 0x084)
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#define P0_DX0LCDLR2 (MCTL_PHY_BASE + 0x2C0)
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#define P0_DX0GTR (MCTL_PHY_BASE + 0x2C8)
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#define P0_DX0MDLR (MCTL_PHY_BASE + 0x2C4)
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#define M0_DRAMTMG8 (MCTL_CTL_BASE + 0x120)
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#define P0_ZQ0CR (MCTL_PHY_BASE + 0x240)
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#define CCM_PLL6_DDR_REG (CCM_PLL_BASE + 0x014)
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#define CCM_DRAMCLK_CFG_REG (CCM_MOD_BASE + 0x084)
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#define CCM_AHB0_SOFT_RST_REG (CCM_MOD_BASE + 0x1a0)
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#define CCM_AHB0_CLK_GAT_REG (CCM_MOD_BASE + 0x180)
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#define SUART_THR (UART_BASE + 0x00)
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#define SUART_USR (UART_BASE + 0x7c)
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#define VDD_SYS_POFF_GATING (R_PRCM_BASE + 0x110)
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#define CNT64_LOW_REG (CNT64_CTRL_REG + 0x04)
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#define CNT64_HIGH_REG (CNT64_CTRL_REG + 0x08)
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#elif defined(CONFIG_ARCH_SUN8IW5P1)
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#define SRAM_DDRFREQ_SIZE (SZ_8K)
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/* register define */
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#define MCTL_COM_BASE ((void *)(0xf1c62000))
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#define MCTL_CTL_BASE ((void *)(0xf1c63000))
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#define CCM_PLL_BASE ((void *)(0xf1c20000))
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#define UART_BASE ((void *)(0xf1c28000))
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#define R_PRCM_BASE ((void *)(0xf1f01400))
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#define R_CPU_CFG_REG ((void *)(0xf1f01c00))
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#define MC_WORK_MODE (MCTL_COM_BASE + 0x00)
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#define MC_MAER (MCTL_COM_BASE + 0x94)
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#define MC_MDFSCR (MCTL_COM_BASE + 0x100)
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#define MC_MDFSMER (MCTL_COM_BASE + 0x104)
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#define MC_MDFSMRMR (MCTL_COM_BASE + 0x108)
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#define PIR (MCTL_CTL_BASE + 0x00)
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#define MC_CLKEN (MCTL_CTL_BASE + 0x0c)
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#define PWRCTL (MCTL_CTL_BASE + 0x04)
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#define PGSR0 (MCTL_CTL_BASE + 0x10)
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#define STATR (MCTL_CTL_BASE + 0x18)
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#define PLLGCR (MCTL_CTL_BASE + 0x40)
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#define PTR1 (MCTL_CTL_BASE + 0x48)
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#define RFSHTMG (MCTL_CTL_BASE + 0x90)
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#define DTCR (MCTL_CTL_BASE + 0xc0)
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#define ODTMAP (MCTL_CTL_BASE + 0x120)
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#define DXnGCR0(x) (MCTL_CTL_BASE + 0x344 + 0x80*(x))
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#define _CCM_PLL_DDR0_REG (CCM_PLL_BASE + 0x20)
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#define _CCM_PLL_DDR1_REG (CCM_PLL_BASE + 0x4C)
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#define CCM_DRAM_CFG_REG (CCM_PLL_BASE + 0xf4)
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#define _CCM_PLL_DDR_CFG_REG (CCM_PLL_BASE + 0xf8)
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#define _CCM_PLL_DDR1_PATTERN_REG (CCM_PLL_BASE + 0x2ac)
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#define _CCM_PLL_DDR0_PATTERN_REG (CCM_PLL_BASE + 0x290)
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#define SUART_THR (UART_BASE + 0x00)
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#define SUART_USR (UART_BASE + 0x7c)
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#define VDD_SYS_POFF_GATING (R_PRCM_BASE + 0x110)
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#define CNT64_CTRL_REG (R_CPU_CFG_REG + 0x280)
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#define CNT64_LOW_REG (R_CPU_CFG_REG + 0x284)
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#define CNT64_HIGH_REG (R_CPU_CFG_REG + 0x288)
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#elif defined(CONFIG_ARCH_SUN8IW6P1)
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#define SRAM_DDRFREQ_SIZE (SZ_8K)
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/* register define */
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#define MCTL_COM_BASE ((void *)(0xf1c62000))
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#define MCTL_CTL_BASE ((void *)(0xf1c63000))
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#define CCM_PLL_BASE ((void *)(0xf1c20000))
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#define R_CPU_CFG_REG ((void *)(0xf1f01c00))
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#define UART_BASE ((void *)(0xf1c28000))
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#define MC_WORK_MODE (MCTL_COM_BASE + 0x00)
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#define MC_MAER (MCTL_COM_BASE + 0x94)
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#define MC_MDFSCR (MCTL_COM_BASE + 0x100)
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#define MC_MDFSMRMR (MCTL_COM_BASE + 0x108)
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#define PWRCTL (MCTL_CTL_BASE + 0x04)
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#define RFSHTMG (MCTL_CTL_BASE + 0x90)
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#define PGCR0 (MCTL_CTL_BASE + 0x100)
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#define PGCR1 (MCTL_CTL_BASE + 0x104)
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#define ODTMAP (MCTL_CTL_BASE + 0x120)
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#define DXnLCDLR1(x) (MCTL_CTL_BASE + 0x308 + 0x80*(x))
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#define DATX0IOCR(x) (MCTL_CTL_BASE + 0x310 + 0x4*(x))
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#define DATX1IOCR(x) (MCTL_CTL_BASE + 0x390 + 0x4*(x))
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#define DATX2IOCR(x) (MCTL_CTL_BASE + 0x410 + 0x4*(x))
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#define DATX3IOCR(x) (MCTL_CTL_BASE + 0x490 + 0x4*(x))
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#define _CCM_PLL_DDR_REG (CCM_PLL_BASE + 0x20)
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#define CCM_DRAM_CFG_REG (CCM_PLL_BASE + 0xf4)
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#define _CCM_PLL_DDR_CFG_REG (CCM_PLL_BASE + 0xf8)
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#define _CCM_PLL_DDR_PATTERN_REG (CCM_PLL_BASE + 0x290)
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#define SUART_THR (UART_BASE + 0x00)
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#define SUART_USR (UART_BASE + 0x7c)
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#define CNT64_CTRL_REG (R_CPU_CFG_REG + 0x280)
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#define CNT64_LOW_REG (R_CPU_CFG_REG + 0x284)
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#define CNT64_HIGH_REG (R_CPU_CFG_REG + 0x288)
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#elif defined(CONFIG_ARCH_SUN8IW7P1)
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#define SRAM_DDRFREQ_SIZE (SZ_8K)
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/* register define */
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#define MCTL_COM_BASE ((void *)(0xf1c62000))
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#define MCTL_CTL_BASE ((void *)(0xf1c63000))
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#define CCM_PLL_BASE ((void *)(0xf1c20000))
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#define R_CPU_CFG_REG ((void *)(0xf1f01c00))
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#define UART_BASE ((void *)(0xf1c28000))
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#define MC_WORK_MODE (MCTL_COM_BASE + 0x00)
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#define PIR (MCTL_CTL_BASE + 0x00)
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#define PWRCTL (MCTL_CTL_BASE + 0x04)
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#define PGSR0 (MCTL_CTL_BASE + 0x10)
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#define STATR (MCTL_CTL_BASE + 0x18)
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#define DTCR (MCTL_CTL_BASE + 0xc0)
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#define ODTMAP (MCTL_CTL_BASE + 0x120)
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#define DXnGCR0(x) (MCTL_CTL_BASE + 0x344 + 0x80*(x))
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#define _CCM_PLL_DDR_REG (CCM_PLL_BASE + 0x20)
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#define CCM_DRAM_CFG_REG (CCM_PLL_BASE + 0xf4)
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#define SUART_THR (UART_BASE + 0x00)
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#define SUART_USR (UART_BASE + 0x7c)
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#define CNT64_CTRL_REG (R_CPU_CFG_REG + 0x280)
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#define CNT64_LOW_REG (R_CPU_CFG_REG + 0x284)
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#define CNT64_HIGH_REG (R_CPU_CFG_REG + 0x288)
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#elif defined(CONFIG_ARCH_SUN8IW8P1)
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/* register define */
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#define MCTL_COM_BASE ((void *)(0xf1c62000))
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#define MCTL_CTL_BASE ((void *)(0xf1c63000))
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#define CCM_PLL_BASE ((void *)(0xf1c20000))
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#elif defined(CONFIG_ARCH_SUN8IW9P1)
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#define SRAM_DDRFREQ_SIZE (SZ_8K)
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/* register define */
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#define MCTL_COM_BASE ((void *)(0xf1c62000))
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#define MCTL_CTL_BASE ((void *)(0xf1c63000))
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#define CCM_PLL_BASE ((void *)(0xf1c20000))
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#define MC_WORK_MODE (MCTL_COM_BASE + 0x00)
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#define MC_MDFSCR (MCTL_COM_BASE + 0x100)
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#define RFSHTMG (MCTL_CTL_BASE + 0x90)
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#define PGCR0 (MCTL_CTL_BASE + 0x100)
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#define ODTMAP (MCTL_CTL_BASE + 0x120)
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#define DXnGCR0(x) (MCTL_CTL_BASE + 0x344 + 0x80*(x))
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#define CCM_DRAM_CFG_REG (CCM_PLL_BASE + 0xf4)
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#define _CCM_PLL_DDR1_REG (CCM_PLL_BASE + 0x4C)
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#endif
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typedef struct __DRAM_PARA {
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unsigned int dram_clk;
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/* dram_type DDR2: 2; DDR3: 3; LPDDR2: 6; LPDDR3: 7; DDR3L: 31 */
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unsigned int dram_type;
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/* [7:0] for CK/CA [15:8] for DX0/1 [23:16] for DX2/3 */
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unsigned int dram_zq;
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unsigned int dram_odt_en;
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/* [31:30]-channel_enable [29:28]-channel_number [27:24]-bank_size [23:16]-row_width [15:8]-bus_width [7:4]-rank [3:0]-page_size */
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unsigned int dram_para1;
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/* [2]-single_chip_DQ_width [1:0]-single_chip_density */
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unsigned int dram_para2;
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unsigned int dram_mr0;
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unsigned int dram_mr1;
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unsigned int dram_mr2;
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unsigned int dram_mr3;
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unsigned int dram_tpr0;
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unsigned int dram_tpr1;
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unsigned int dram_tpr2;
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unsigned int dram_tpr3;
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/* [0]-1T/2T [4]-half_dq */
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unsigned int dram_tpr4;
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unsigned int dram_tpr5;
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/* [0]-wake_branch */
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unsigned int dram_tpr6;
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unsigned int dram_tpr7;
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unsigned int dram_tpr8;
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unsigned int dram_tpr9;
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unsigned int dram_tpr10;
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unsigned int dram_tpr11;
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unsigned int dram_tpr12;
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unsigned int dram_tpr13;
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} __dram_para_t;
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static inline unsigned long ddr_save_sp(unsigned long new_sp)
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{
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unsigned long old_sp;
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asm volatile ("mov %0, sp" : "=r" (old_sp));
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asm volatile ("mov sp, %0" : : "r" (new_sp));
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return old_sp;
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}
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/* sp define */
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#define SRAM_DDRFREQ_SP_ADDR (SRAM_DDRFREQ_OFFSET + SRAM_DDRFREQ_SIZE)
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#define DDR_SAVE_SP(save_sp) do { save_sp = ddr_save_sp(((unsigned long)SRAM_DDRFREQ_SP_ADDR)); } while (0)
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#define DDR_RESTORE_SP(save_sp) do { ddr_save_sp(save_sp); } while (0)
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#define mctl_read_w(n) (*((volatile unsigned int *)(n)))
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#define mctl_write_w(c, n) (*((volatile unsigned int *)(n)) = (c))
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#if defined(CONFIG_ARCH_SUN9IW1P1) || defined(CONFIG_ARCH_SUN8IW7P1) || defined(CONFIG_DEVFREQ_DRAM_FREQ_LOW_POWER_SW) || defined(CONFIG_DEVFREQ_DRAM_FREQ_CFS_SW)
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extern int __sram mdfs_main(unsigned int jump, __dram_para_t *dram_para,
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unsigned int pll_para_from_dram, unsigned int div);
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#endif
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#ifdef CONFIG_ARCH_SUN9IW1P1
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extern void prefetch_and_prediction_disable(void);
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extern void prefetch_and_prediction_enable(void);
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#endif
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#endif /* __MDFS_H__ */
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