/*
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* Copyright (C) 2016 Allwinner.
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* zhouhuacai <zhouhuacai@allwinnertech.com>
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* wangwei <wangwei@allwinnertech.com>
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*
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* SUNXI TWI Controller Definition
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _SUNXI_I2C_H_
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#define _SUNXI_I2C_H_
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/* status or interrupt source */
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/*------------------------------------------------------------------------------
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* Code Status
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* 00h Bus error
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* 08h START condition transmitted
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* 10h Repeated START condition transmitted
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* 18h Address + Write bit transmitted, ACK received
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* 20h Address + Write bit transmitted, ACK not received
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* 28h Data byte transmitted in master mode, ACK received
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* 30h Data byte transmitted in master mode, ACK not received
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* 38h Arbitration lost in address or data byte
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* 40h Address + Read bit transmitted, ACK received
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* 48h Address + Read bit transmitted, ACK not received
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* 50h Data byte received in master mode, ACK transmitted
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* 58h Data byte received in master mode, not ACK transmitted
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* 60h Slave address + Write bit received, ACK transmitted
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* 68h Arbitration lost in address as master, slave address + Write bit received, ACK transmitted
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* 70h General Call address received, ACK transmitted
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* 78h Arbitration lost in address as master, General Call address received, ACK transmitted
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* 80h Data byte received after slave address received, ACK transmitted
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* 88h Data byte received after slave address received, not ACK transmitted
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* 90h Data byte received after General Call received, ACK transmitted
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* 98h Data byte received after General Call received, not ACK transmitted
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* A0h STOP or repeated START condition received in slave mode
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* A8h Slave address + Read bit received, ACK transmitted
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* B0h Arbitration lost in address as master, slave address + Read bit received, ACK transmitted
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* B8h Data byte transmitted in slave mode, ACK received
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* C0h Data byte transmitted in slave mode, ACK not received
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* C8h Last byte transmitted in slave mode, ACK received
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* D0h Second Address byte + Write bit transmitted, ACK received
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* D8h Second Address byte + Write bit transmitted, ACK not received
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* F8h No relevant status information or no interrupt
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*-----------------------------------------------------------------------------*/
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#define I2C_START_TRANSMIT 0x08
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#define I2C_RESTART_TRANSMIT 0x10
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#define I2C_ADDRWRITE_ACK 0x18
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#define I2C_ADDRREAD_ACK 0x40
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#define I2C_DATAWRITE_ACK 0x28
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#define I2C_READY 0xf8
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#define I2C_DATAREAD_NACK 0x58
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#define I2C_DATAREAD_ACK 0x50
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#define SUNXI_I2C_OK 0
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#define SUNXI_I2C_FAIL -1
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#define SUNXI_I2C_RETRY -2
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#define SUNXI_I2C_SFAIL -3
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#define SUNXI_I2C_TFAIL -4
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#define SUNXI_I2C_TOUT -5
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#define I2C_WRITE 0
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#define I2C_READ 1
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/* TWI Soft Reset Register Bit Fields & Masks */
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#define TWI_SRST_SRST (0x1<<0)
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/* TWI Control Register Bit Fields & Masks, default value: 0x0000_0000*/
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#define TWI_CTL_ACK (0x1<<2)
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#define TWI_CTL_INTFLG (0x1<<3)
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#define TWI_CTL_STP (0x1<<4)
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#define TWI_CTL_STA (0x1<<5)
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#define TWI_CTL_BUSEN (0x1<<6)
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#define TWI_CTL_INTEN (0x1<<7)
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/* 31:8 bit reserved */
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/* twi line control register -default value: 0x0000_003a */
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#define TWI_LCR_SDA_EN (0x01<<0)
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#define TWI_LCR_SDA_CTL (0x01<<1)
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#define TWI_LCR_SCL_EN (0x01<<2)
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#define TWI_LCR_SCL_CTL (0x01<<3)
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#define TWI_LCR_SDA_STATE_MASK (0x01<<4)
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#define TWI_LCR_SCL_STATE_MASK (0x01<<5)
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#define TWI_STAT_IDLE (0xF8)
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#define TWI_LCR_NORM_STATUS (0x30)
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#define TWI_CONTROL_OFFSET 0x400
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#define SUNXI_I2C_CONTROLLER 5
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struct sunxi_twi_reg
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{
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volatile unsigned int addr; /* slave address */
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volatile unsigned int xaddr; /* extend address */
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volatile unsigned int data; /* data */
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volatile unsigned int ctl; /* control */
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volatile unsigned int status; /* status */
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volatile unsigned int clk; /* clock */
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volatile unsigned int srst; /* soft reset */
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volatile unsigned int eft; /* enhanced future */
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volatile unsigned int lcr; /* line control */
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volatile unsigned int dvfs; /* dvfs control */
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};
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enum {
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SUNXI_PHY_I2C0 = 0,
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SUNXI_PHY_I2C1,
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SUNXI_PHY_I2C2,
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SUNXI_PHY_I2C3,
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SUNXI_PHY_I2C4,
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SUNXI_PHY_I2C5,
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SUNXI_PHY_R_I2C0,
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SUNXI_PHY_R_I2C1,
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/*The new i2c bus must be added before SUNXI_PHY_I2C_BUS_MAX*/
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SUNXI_PHY_I2C_BUS_MAX,
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};
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enum {
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#ifdef CONFIG_I2C0_ENABLE
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SUNXI_VIR_I2C0,
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#endif
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#ifdef CONFIG_I2C1_ENABLE
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SUNXI_VIR_I2C1,
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#endif
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#ifdef CONFIG_I2C2_ENABLE
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SUNXI_VIR_I2C2,
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#endif
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#ifdef CONFIG_I2C3_ENABLE
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SUNXI_VIR_I2C3,
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#endif
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#ifdef CONFIG_I2C4_ENABLE
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SUNXI_VIR_I2C4,
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#endif
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#ifdef CONFIG_I2C5_ENABLE
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SUNXI_VIR_I2C5,
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#endif
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#ifdef CONFIG_R_I2C0_ENABLE
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SUNXI_VIR_R_I2C0,
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#endif
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#ifdef CONFIG_R_I2C1_ENABLE
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SUNXI_VIR_R_I2C1,
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#endif
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/*The new i2c bus must be added before SUNXI_VIR_I2C_BUS_MAX*/
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SUNXI_VIR_I2C_BUS_MAX,
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};
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#endif /* _SUNXI_I2C_H_ */
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