/*
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* (C) Copyright 2018
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* wangwei <wangwei@allwinnertech.com>
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __boot0_v2_h
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#define __boot0_v2_h
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#include <linux/types.h>
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#include <spare_head.h>
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#define BOOT0_MAGIC "eGON.BT0"
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#define SYS_PARA_LOG 0x4d415244
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/******************************************************************************/
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/* file head of Boot */
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/******************************************************************************/
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typedef struct _Boot_file_head
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{
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__u32 jump_instruction; /* one intruction jumping to real code */
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__u8 magic[MAGIC_SIZE]; /* ="eGON.BT0" */
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__u32 check_sum; /* generated by PC */
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__u32 length; /* generated by PC */
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__u32 pub_head_size; /* the size of boot_file_head_t */
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__u8 pub_head_vsn[4]; /* the version of boot_file_head_t */
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__u32 ret_addr; /* the return value */
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__u32 run_addr; /* run addr */
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__u32 boot_cpu; /* eGON version */
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__u8 platform[8]; /* platform information */
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}boot_file_head_t;
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/******************************************************************************/
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/* file head of Boot0 */
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/******************************************************************************/
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typedef struct _boot0_private_head_t
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{
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__u32 prvt_head_size;
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/*debug_mode = 0 : do not print any message,debug_mode = 1 ,print debug message*/
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__u8 debug_mode;
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/*0:axp, 1: no axp */
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__u8 power_mode;
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__u8 reserve[2];
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/*DRAM patameters for initialising dram. Original values is arbitrary*/
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unsigned int dram_para[32];
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/*uart: num & uart pin*/
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__s32 uart_port;
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normal_gpio_cfg uart_ctrl[2];
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/* jtag: 1 : enable, 0 : disable */
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__s32 enable_jtag;
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normal_gpio_cfg jtag_gpio[5];
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/* nand/mmc pin*/
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normal_gpio_cfg storage_gpio[32];
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/*reserve data*/
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char storage_data[512 - sizeof(normal_gpio_cfg) * 32];
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}boot0_private_head_t;
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typedef struct _boot0_file_head_t
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{
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boot_file_head_t boot_head;
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boot0_private_head_t prvt_head;
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char hash[64];
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}boot0_file_head_t;
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extern const boot0_file_head_t BT0_head;
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#endif
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