// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2015 Stefan Roese <sr@denx.de>
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*/
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#include <common.h>
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#include <i2c.h>
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#include <miiphy.h>
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#include <netdev.h>
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#include <asm/io.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/soc.h>
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#include "../drivers/ddr/marvell/a38x/ddr3_a38x_topology.h"
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#include <../serdes/a38x/high_speed_env_spec.h>
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DECLARE_GLOBAL_DATA_PTR;
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#define ETH_PHY_CTRL_REG 0
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#define ETH_PHY_CTRL_POWER_DOWN_BIT 11
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#define ETH_PHY_CTRL_POWER_DOWN_MASK (1 << ETH_PHY_CTRL_POWER_DOWN_BIT)
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/*
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* Those values and defines are taken from the Marvell U-Boot version
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* "u-boot-2013.01-2016_T1.0.eng_drop_v10"
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*/
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#define DB_AMC_88F68XX_GPP_OUT_ENA_LOW \
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(~(BIT(29)))
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#define DB_AMC_88F68XX_GPP_OUT_ENA_MID \
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(~(BIT(12) | BIT(17) | BIT(18) | BIT(20) | BIT(21)))
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#define DB_AMC_88F68XX_GPP_OUT_VAL_LOW (BIT(29))
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#define DB_AMC_88F68XX_GPP_OUT_VAL_MID 0x0
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#define DB_AMC_88F68XX_GPP_OUT_VAL_HIGH 0x0
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#define DB_AMC_88F68XX_GPP_POL_LOW 0x0
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#define DB_AMC_88F68XX_GPP_POL_MID 0x0
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static struct serdes_map board_serdes_map[] = {
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{PEX0, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0},
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{DEFAULT_SERDES, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
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{DEFAULT_SERDES, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
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{DEFAULT_SERDES, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
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{SGMII1, SERDES_SPEED_1_25_GBPS, SERDES_DEFAULT_MODE, 0, 0},
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{SGMII2, SERDES_SPEED_1_25_GBPS, SERDES_DEFAULT_MODE, 0, 0}
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};
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int hws_board_topology_load(struct serdes_map **serdes_map_array, u8 *count)
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{
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*serdes_map_array = board_serdes_map;
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*count = ARRAY_SIZE(board_serdes_map);
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return 0;
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}
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/*
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* Define the DDR layout / topology here in the board file. This will
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* be used by the DDR3 init code in the SPL U-Boot version to configure
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* the DDR3 controller.
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*/
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static struct hws_topology_map board_topology_map = {
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0x1, /* active interfaces */
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/* cs_mask, mirror, dqs_swap, ck_swap X PUPs */
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{ { { {0x1, 0, 0, 0},
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{0x1, 0, 0, 0},
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{0x1, 0, 0, 0},
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{0x1, 0, 0, 0},
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{0x1, 0, 0, 0} },
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SPEED_BIN_DDR_1866L, /* speed_bin */
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BUS_WIDTH_8, /* memory_width */
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MEM_2G, /* mem_size */
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DDR_FREQ_800, /* frequency */
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0, 0, /* cas_wl cas_l */
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HWS_TEMP_LOW, /* temperature */
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HWS_TIM_DEFAULT} }, /* timing */
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5, /* Num Of Bus Per Interface*/
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BUS_MASK_32BIT /* Busses mask */
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};
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struct hws_topology_map *ddr3_get_topology_map(void)
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{
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/* Return the board topology as defined in the board code */
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return &board_topology_map;
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}
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int board_early_init_f(void)
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{
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/* Configure MPP */
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writel(0x11111111, MVEBU_MPP_BASE + 0x00);
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writel(0x11111111, MVEBU_MPP_BASE + 0x04);
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writel(0x55066011, MVEBU_MPP_BASE + 0x08);
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writel(0x05055550, MVEBU_MPP_BASE + 0x0c);
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writel(0x05055555, MVEBU_MPP_BASE + 0x10);
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writel(0x01106565, MVEBU_MPP_BASE + 0x14);
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writel(0x40000000, MVEBU_MPP_BASE + 0x18);
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writel(0x00004444, MVEBU_MPP_BASE + 0x1c);
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/* Set GPP Out value */
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writel(DB_AMC_88F68XX_GPP_OUT_VAL_LOW, MVEBU_GPIO0_BASE + 0x00);
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writel(DB_AMC_88F68XX_GPP_OUT_VAL_MID, MVEBU_GPIO1_BASE + 0x00);
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/* Set GPP Polarity */
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writel(DB_AMC_88F68XX_GPP_POL_LOW, MVEBU_GPIO0_BASE + 0x0c);
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writel(DB_AMC_88F68XX_GPP_POL_MID, MVEBU_GPIO1_BASE + 0x0c);
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/* Set GPP Out Enable */
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writel(DB_AMC_88F68XX_GPP_OUT_ENA_LOW, MVEBU_GPIO0_BASE + 0x04);
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writel(DB_AMC_88F68XX_GPP_OUT_ENA_MID, MVEBU_GPIO1_BASE + 0x04);
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return 0;
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}
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int board_init(void)
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{
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/* adress of boot parameters */
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gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
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return 0;
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}
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int checkboard(void)
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{
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puts("Board: Marvell DB-88F6820-AMC\n");
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return 0;
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}
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int board_eth_init(bd_t *bis)
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{
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cpu_eth_init(bis); /* Built in controller(s) come first */
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return pci_eth_init(bis);
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}
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