/*
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* Copyright © 2016 Broadcom
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*/
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#include "compiler/v3d_compiler.h"
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#include "qpu/qpu_instr.h"
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#include "qpu/qpu_disasm.h"
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static inline struct qpu_reg
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qpu_reg(int index)
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{
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struct qpu_reg reg = {
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.magic = false,
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.index = index,
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};
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return reg;
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}
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static inline struct qpu_reg
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qpu_magic(enum v3d_qpu_waddr waddr)
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{
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struct qpu_reg reg = {
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.magic = true,
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.index = waddr,
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};
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return reg;
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}
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static inline struct qpu_reg
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qpu_acc(int acc)
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{
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return qpu_magic(V3D_QPU_WADDR_R0 + acc);
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}
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struct v3d_qpu_instr
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v3d_qpu_nop(void)
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{
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struct v3d_qpu_instr instr = {
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.type = V3D_QPU_INSTR_TYPE_ALU,
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.alu = {
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.add = {
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.op = V3D_QPU_A_NOP,
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.waddr = V3D_QPU_WADDR_NOP,
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.magic_write = true,
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},
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.mul = {
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.op = V3D_QPU_M_NOP,
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.waddr = V3D_QPU_WADDR_NOP,
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.magic_write = true,
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},
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}
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};
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return instr;
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}
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static struct qinst *
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vir_nop(void)
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{
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struct qreg undef = { QFILE_NULL, 0 };
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struct qinst *qinst = vir_add_inst(V3D_QPU_A_NOP, undef, undef, undef);
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return qinst;
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}
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static struct qinst *
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new_qpu_nop_before(struct qinst *inst)
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{
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struct qinst *q = vir_nop();
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list_addtail(&q->link, &inst->link);
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return q;
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}
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static void
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new_ldunif_instr(struct qinst *inst, int i)
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{
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struct qinst *ldunif = new_qpu_nop_before(inst);
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ldunif->qpu.sig.ldunif = true;
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assert(inst->src[i].file == QFILE_UNIF);
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ldunif->uniform = inst->src[i].index;
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}
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/**
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* Allocates the src register (accumulator or register file) into the RADDR
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* fields of the instruction.
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*/
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static void
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set_src(struct v3d_qpu_instr *instr, enum v3d_qpu_mux *mux, struct qpu_reg src)
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{
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if (src.magic) {
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assert(src.index >= V3D_QPU_WADDR_R0 &&
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src.index <= V3D_QPU_WADDR_R5);
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*mux = src.index - V3D_QPU_WADDR_R0 + V3D_QPU_MUX_R0;
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return;
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}
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if (instr->alu.add.a != V3D_QPU_MUX_A &&
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instr->alu.add.b != V3D_QPU_MUX_A &&
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instr->alu.mul.a != V3D_QPU_MUX_A &&
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instr->alu.mul.b != V3D_QPU_MUX_A) {
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instr->raddr_a = src.index;
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*mux = V3D_QPU_MUX_A;
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} else {
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if (instr->raddr_a == src.index) {
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*mux = V3D_QPU_MUX_A;
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} else {
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assert(!(instr->alu.add.a == V3D_QPU_MUX_B &&
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instr->alu.add.b == V3D_QPU_MUX_B &&
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instr->alu.mul.a == V3D_QPU_MUX_B &&
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instr->alu.mul.b == V3D_QPU_MUX_B) ||
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src.index == instr->raddr_b);
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instr->raddr_b = src.index;
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*mux = V3D_QPU_MUX_B;
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}
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}
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}
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static void
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v3d_generate_code_block(struct v3d_compile *c,
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struct qblock *block,
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struct qpu_reg *temp_registers)
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{
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int last_vpm_read_index = -1;
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vir_for_each_inst(qinst, block) {
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#if 0
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fprintf(stderr, "translating qinst to qpu: ");
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vir_dump_inst(c, qinst);
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fprintf(stderr, "\n");
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#endif
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struct qinst *temp;
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if (vir_has_implicit_uniform(qinst)) {
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int src = vir_get_implicit_uniform_src(qinst);
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assert(qinst->src[src].file == QFILE_UNIF);
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qinst->uniform = qinst->src[src].index;
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c->num_uniforms++;
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}
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int nsrc = vir_get_non_sideband_nsrc(qinst);
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struct qpu_reg src[ARRAY_SIZE(qinst->src)];
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bool emitted_ldunif = false;
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for (int i = 0; i < nsrc; i++) {
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int index = qinst->src[i].index;
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switch (qinst->src[i].file) {
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case QFILE_REG:
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src[i] = qpu_reg(qinst->src[i].index);
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break;
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case QFILE_MAGIC:
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src[i] = qpu_magic(qinst->src[i].index);
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break;
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case QFILE_NULL:
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case QFILE_LOAD_IMM:
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src[i] = qpu_acc(0);
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break;
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case QFILE_TEMP:
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src[i] = temp_registers[index];
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break;
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case QFILE_UNIF:
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if (!emitted_ldunif) {
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new_ldunif_instr(qinst, i);
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c->num_uniforms++;
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emitted_ldunif = true;
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}
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src[i] = qpu_acc(5);
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break;
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case QFILE_SMALL_IMM:
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abort(); /* XXX */
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#if 0
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src[i].mux = QPU_MUX_SMALL_IMM;
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src[i].addr = qpu_encode_small_immediate(qinst->src[i].index);
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/* This should only have returned a valid
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* small immediate field, not ~0 for failure.
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*/
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assert(src[i].addr <= 47);
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#endif
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break;
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case QFILE_VPM:
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assert((int)qinst->src[i].index >=
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last_vpm_read_index);
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(void)last_vpm_read_index;
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last_vpm_read_index = qinst->src[i].index;
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temp = new_qpu_nop_before(qinst);
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temp->qpu.sig.ldvpm = true;
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src[i] = qpu_acc(3);
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break;
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case QFILE_TLB:
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case QFILE_TLBU:
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unreachable("bad vir src file");
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}
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}
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struct qpu_reg dst;
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switch (qinst->dst.file) {
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case QFILE_NULL:
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dst = qpu_magic(V3D_QPU_WADDR_NOP);
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break;
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case QFILE_REG:
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dst = qpu_reg(qinst->dst.index);
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break;
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case QFILE_MAGIC:
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dst = qpu_magic(qinst->dst.index);
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break;
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case QFILE_TEMP:
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dst = temp_registers[qinst->dst.index];
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break;
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case QFILE_VPM:
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dst = qpu_magic(V3D_QPU_WADDR_VPM);
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break;
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case QFILE_TLB:
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dst = qpu_magic(V3D_QPU_WADDR_TLB);
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break;
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case QFILE_TLBU:
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dst = qpu_magic(V3D_QPU_WADDR_TLBU);
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break;
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case QFILE_UNIF:
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case QFILE_SMALL_IMM:
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case QFILE_LOAD_IMM:
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assert(!"not reached");
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break;
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}
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if (qinst->qpu.type == V3D_QPU_INSTR_TYPE_ALU) {
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if (v3d_qpu_sig_writes_address(c->devinfo,
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&qinst->qpu.sig)) {
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assert(qinst->qpu.alu.add.op == V3D_QPU_A_NOP);
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assert(qinst->qpu.alu.mul.op == V3D_QPU_M_NOP);
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qinst->qpu.sig_addr = dst.index;
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qinst->qpu.sig_magic = dst.magic;
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} else if (qinst->qpu.alu.add.op != V3D_QPU_A_NOP) {
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assert(qinst->qpu.alu.mul.op == V3D_QPU_M_NOP);
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if (nsrc >= 1) {
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set_src(&qinst->qpu,
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&qinst->qpu.alu.add.a, src[0]);
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}
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if (nsrc >= 2) {
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set_src(&qinst->qpu,
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&qinst->qpu.alu.add.b, src[1]);
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}
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qinst->qpu.alu.add.waddr = dst.index;
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qinst->qpu.alu.add.magic_write = dst.magic;
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} else {
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if (nsrc >= 1) {
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set_src(&qinst->qpu,
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&qinst->qpu.alu.mul.a, src[0]);
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}
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if (nsrc >= 2) {
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set_src(&qinst->qpu,
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&qinst->qpu.alu.mul.b, src[1]);
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}
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qinst->qpu.alu.mul.waddr = dst.index;
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qinst->qpu.alu.mul.magic_write = dst.magic;
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}
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} else {
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assert(qinst->qpu.type == V3D_QPU_INSTR_TYPE_BRANCH);
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}
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}
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}
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static void
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v3d_dump_qpu(struct v3d_compile *c)
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{
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fprintf(stderr, "%s prog %d/%d QPU:\n",
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vir_get_stage_name(c),
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c->program_id, c->variant_id);
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for (int i = 0; i < c->qpu_inst_count; i++) {
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const char *str = v3d_qpu_disasm(c->devinfo, c->qpu_insts[i]);
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fprintf(stderr, "0x%016"PRIx64" %s\n", c->qpu_insts[i], str);
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}
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fprintf(stderr, "\n");
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}
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void
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v3d_vir_to_qpu(struct v3d_compile *c, struct qpu_reg *temp_registers)
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{
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/* Reset the uniform count to how many will be actually loaded by the
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* generated QPU code.
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*/
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c->num_uniforms = 0;
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vir_for_each_block(block, c)
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v3d_generate_code_block(c, block, temp_registers);
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uint32_t cycles = v3d_qpu_schedule_instructions(c);
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c->qpu_insts = rzalloc_array(c, uint64_t, c->qpu_inst_count);
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int i = 0;
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vir_for_each_inst_inorder(inst, c) {
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bool ok = v3d_qpu_instr_pack(c->devinfo, &inst->qpu,
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&c->qpu_insts[i++]);
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assert(ok); (void) ok;
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}
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assert(i == c->qpu_inst_count);
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if (V3D_DEBUG & V3D_DEBUG_SHADERDB) {
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fprintf(stderr, "SHADER-DB: %s prog %d/%d: %d estimated cycles\n",
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vir_get_stage_name(c),
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c->program_id, c->variant_id,
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cycles);
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}
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if (V3D_DEBUG & (V3D_DEBUG_QPU |
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v3d_debug_flag_for_shader_stage(c->s->info.stage))) {
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v3d_dump_qpu(c);
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}
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qpu_validate(c);
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free(temp_registers);
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}
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