/*
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* include/linux/sunxi-gpio.h
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*
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* (C) Copyright 2015-2020
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* Allwinner Technology Co., Ltd. <www.allwinnertech.com>
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* Wim Hwang <huangwei@allwinnertech.com>
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*
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* sunxi gpio utils
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*/
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#ifndef __SW_GPIO_H
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#define __SW_GPIO_H
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#define SUNXI_PINCTRL "pio"
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#define SUNXI_R_PINCTRL "r_pio"
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#include <linux/pinctrl/pinconf-generic.h>
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/* pin group base number name space,
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* the max pin number : 26*32=832.
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*/
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#define SUNXI_BANK_SIZE 32
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#define SUNXI_PA_BASE 0
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#define SUNXI_PB_BASE 32
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#define SUNXI_PC_BASE 64
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#define SUNXI_PD_BASE 96
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#define SUNXI_PE_BASE 128
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#define SUNXI_PF_BASE 160
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#define SUNXI_PG_BASE 192
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#define SUNXI_PH_BASE 224
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#define SUNXI_PI_BASE 256
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#define SUNXI_PJ_BASE 288
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#define SUNXI_PK_BASE 320
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#define SUNXI_PL_BASE 352
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#define SUNXI_PM_BASE 384
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#define SUNXI_PN_BASE 416
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#define SUNXI_PO_BASE 448
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#define AXP_PIN_BASE 1024
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#define SUNXI_PIN_NAME_MAX_LEN 8
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/* sunxi gpio name space */
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#define GPIOA(n) (SUNXI_PA_BASE + (n))
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#define GPIOB(n) (SUNXI_PB_BASE + (n))
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#define GPIOC(n) (SUNXI_PC_BASE + (n))
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#define GPIOD(n) (SUNXI_PD_BASE + (n))
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#define GPIOE(n) (SUNXI_PE_BASE + (n))
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#define GPIOF(n) (SUNXI_PF_BASE + (n))
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#define GPIOG(n) (SUNXI_PG_BASE + (n))
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#define GPIOH(n) (SUNXI_PH_BASE + (n))
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#define GPIOI(n) (SUNXI_PI_BASE + (n))
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#define GPIOJ(n) (SUNXI_PJ_BASE + (n))
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#define GPIOK(n) (SUNXI_PK_BASE + (n))
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#define GPIOL(n) (SUNXI_PL_BASE + (n))
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#define GPIOM(n) (SUNXI_PM_BASE + (n))
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#define GPION(n) (SUNXI_PN_BASE + (n))
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#define GPIOO(n) (SUNXI_PO_BASE + (n))
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#define GPIO_AXP(n) (AXP_PIN_BASE + (n))
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/* sunxi specific input/output/eint functions */
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#define SUNXI_PIN_INPUT_FUNC (0)
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#define SUNXI_PIN_OUTPUT_FUNC (1)
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#define SUNXI_PIN_EINT_FUNC (6)
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#define SUNXI_PIN_IO_DISABLE (7)
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/* axp group base number name space,
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* axp pinctrl number space coherent to sunxi-pinctrl.
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*/
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#define AXP_PINCTRL "axp-pinctrl"
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#define AXP_CFG_GRP (0xFFFF)
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#define AXP_PIN_INPUT_FUNC (0)
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#define AXP_PIN_OUTPUT_FUNC (1)
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#define IS_AXP_PIN(pin) (pin >= AXP_PIN_BASE)
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/* sunxi specific pull up/down */
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enum sunxi_pull_up_down {
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SUNXI_PULL_DISABLE = 0,
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SUNXI_PULL_UP,
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SUNXI_PULL_DOWN,
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};
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/* sunxi specific data types */
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enum sunxi_data_type {
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SUNXI_DATA_LOW = 0,
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SUNXI_DATA_HIGH = 0,
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};
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/* sunxi specific pull status */
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enum sunxi_pin_pull {
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SUNXI_PIN_PULL_DISABLE = 0x00,
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SUNXI_PIN_PULL_UP = 0x01,
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SUNXI_PIN_PULL_DOWN = 0x02,
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SUNXI_PIN_PULL_RESERVED = 0x03,
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};
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/* sunxi specific driver levels */
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enum sunxi_pin_drv_level {
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SUNXI_DRV_LEVEL0 = 10,
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SUNXI_DRV_LEVEL1 = 20,
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SUNXI_DRV_LEVEL2 = 30,
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SUNXI_DRV_LEVEL3 = 40,
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};
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/* sunxi specific data bit status */
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enum sunxi_pin_data_status {
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SUNXI_PIN_DATA_LOW = 0x00,
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SUNXI_PIN_DATA_HIGH = 0x01,
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};
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/* sunxi pin interrupt trigger mode */
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enum sunxi_pin_int_trigger_mode {
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SUNXI_PIN_EINT_POSITIVE_EDGE = 0x0,
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SUNXI_PIN_EINT_NEGATIVE_EDGE = 0x1,
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SUNXI_PIN_EINT_HIGN_LEVEL = 0x2,
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SUNXI_PIN_EINT_LOW_LEVEL = 0x3,
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SUNXI_PIN_EINT_DOUBLE_EDGE = 0x4
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};
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/* the source clock of pin int */
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enum sunxi_pin_int_source_clk {
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SUNXI_PIN_INT_SRC_CLK_32K = 0x0,
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SUNXI_PIN_INT_SRC_CLK_24M = 0x1
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};
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/*
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* pin configuration (pull up/down and drive strength) type and its value are
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* packed together into a 32-bits. The lower 8-bits represent the configuration
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* type and the upper 24-bits hold the value of the configuration type.
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*/
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#define SUNXI_PINCFG_PACK(type, value) (((value) << 8) | (type & 0xFF))
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#define SUNXI_PINCFG_UNPACK_TYPE(cfg) ((cfg) & 0xFF)
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#define SUNXI_PINCFG_UNPACK_VALUE(cfg) (((cfg) & 0xFFFFFF00) >> 8)
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static inline int sunxi_gpio_to_name(int gpio, char *name)
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{
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int bank, index;
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if (!name)
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return -EINVAL;
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if (IS_AXP_PIN(gpio)) {
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/* axp gpio name like this : GPIO0/GPIO1/.. */
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index = gpio - AXP_PIN_BASE;
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sprintf(name, "GPIO%d", index);
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} else {
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/* sunxi gpio name like this : PA0/PA1/PB0 */
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bank = gpio / SUNXI_BANK_SIZE;
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index = gpio % SUNXI_BANK_SIZE;
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sprintf(name, "P%c%d", ('A' + bank), index);
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}
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return 0;
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}
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/* pio end, invalid macro */
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#define GPIO_INDEX_INVALID (0xFFFFFFF0)
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#define GPIO_CFG_INVALID (0xEEEEEEEE)
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#define GPIO_PULL_INVALID (0xDDDDDDDD)
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#define GPIO_DRVLVL_INVALID (0xCCCCCCCC)
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#define IRQ_NUM_INVALID (0xFFFFFFFF)
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#define AXP_PORT_VAL (0x0000FFFF)
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/* pio default macro */
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#define GPIO_PULL_DEFAULT ((u32)-1)
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#define GPIO_DRVLVL_DEFAULT ((u32)-1)
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#define GPIO_DATA_DEFAULT ((u32)-1)
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/*
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* struct gpio_config - gpio config info
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* @gpio: gpio global index, must be unique
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* @mul_sel: multi sel val: 0 - input, 1 - output.
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* @pull: pull val: 0 - pull up/down disable, 1 - pull up
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* @drv_level: driver level val: 0 - level 0, 1 - level 1
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* @data: data val: 0 - low, 1 - high, only valid when mul_sel is input/output
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*/
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struct gpio_config {
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u32 gpio;
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u32 mul_sel;
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u32 pull;
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u32 drv_level;
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u32 data;
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};
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#endif
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