/*
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* Copyright (C) 2016 The Android Open Source Project
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#include "jni_macro_assembler_x86_64.h"
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#include "base/casts.h"
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#include "base/memory_region.h"
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#include "entrypoints/quick/quick_entrypoints.h"
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#include "thread.h"
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namespace art {
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namespace x86_64 {
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static dwarf::Reg DWARFReg(Register reg) {
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return dwarf::Reg::X86_64Core(static_cast<int>(reg));
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}
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static dwarf::Reg DWARFReg(FloatRegister reg) {
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return dwarf::Reg::X86_64Fp(static_cast<int>(reg));
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}
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constexpr size_t kFramePointerSize = 8;
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#define __ asm_.
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void X86_64JNIMacroAssembler::BuildFrame(size_t frame_size,
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ManagedRegister method_reg,
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ArrayRef<const ManagedRegister> spill_regs,
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const ManagedRegisterEntrySpills& entry_spills) {
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DCHECK_EQ(CodeSize(), 0U); // Nothing emitted yet.
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cfi().SetCurrentCFAOffset(8); // Return address on stack.
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CHECK_ALIGNED(frame_size, kStackAlignment);
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int gpr_count = 0;
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for (int i = spill_regs.size() - 1; i >= 0; --i) {
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x86_64::X86_64ManagedRegister spill = spill_regs[i].AsX86_64();
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if (spill.IsCpuRegister()) {
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__ pushq(spill.AsCpuRegister());
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gpr_count++;
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cfi().AdjustCFAOffset(kFramePointerSize);
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cfi().RelOffset(DWARFReg(spill.AsCpuRegister().AsRegister()), 0);
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}
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}
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// return address then method on stack.
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int64_t rest_of_frame = static_cast<int64_t>(frame_size)
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- (gpr_count * kFramePointerSize)
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- kFramePointerSize /*return address*/;
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__ subq(CpuRegister(RSP), Immediate(rest_of_frame));
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cfi().AdjustCFAOffset(rest_of_frame);
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// spill xmms
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int64_t offset = rest_of_frame;
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for (int i = spill_regs.size() - 1; i >= 0; --i) {
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x86_64::X86_64ManagedRegister spill = spill_regs[i].AsX86_64();
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if (spill.IsXmmRegister()) {
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offset -= sizeof(double);
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__ movsd(Address(CpuRegister(RSP), offset), spill.AsXmmRegister());
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cfi().RelOffset(DWARFReg(spill.AsXmmRegister().AsFloatRegister()), offset);
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}
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}
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static_assert(static_cast<size_t>(kX86_64PointerSize) == kFramePointerSize,
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"Unexpected frame pointer size.");
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__ movq(Address(CpuRegister(RSP), 0), method_reg.AsX86_64().AsCpuRegister());
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for (const ManagedRegisterSpill& spill : entry_spills) {
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if (spill.AsX86_64().IsCpuRegister()) {
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if (spill.getSize() == 8) {
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__ movq(Address(CpuRegister(RSP), frame_size + spill.getSpillOffset()),
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spill.AsX86_64().AsCpuRegister());
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} else {
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CHECK_EQ(spill.getSize(), 4);
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__ movl(Address(CpuRegister(RSP), frame_size + spill.getSpillOffset()),
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spill.AsX86_64().AsCpuRegister());
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}
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} else {
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if (spill.getSize() == 8) {
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__ movsd(Address(CpuRegister(RSP), frame_size + spill.getSpillOffset()),
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spill.AsX86_64().AsXmmRegister());
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} else {
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CHECK_EQ(spill.getSize(), 4);
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__ movss(Address(CpuRegister(RSP), frame_size + spill.getSpillOffset()),
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spill.AsX86_64().AsXmmRegister());
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}
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}
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}
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}
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void X86_64JNIMacroAssembler::RemoveFrame(size_t frame_size,
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ArrayRef<const ManagedRegister> spill_regs,
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bool may_suspend ATTRIBUTE_UNUSED) {
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CHECK_ALIGNED(frame_size, kStackAlignment);
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cfi().RememberState();
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int gpr_count = 0;
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// unspill xmms
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int64_t offset = static_cast<int64_t>(frame_size)
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- (spill_regs.size() * kFramePointerSize)
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- 2 * kFramePointerSize;
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for (size_t i = 0; i < spill_regs.size(); ++i) {
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x86_64::X86_64ManagedRegister spill = spill_regs[i].AsX86_64();
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if (spill.IsXmmRegister()) {
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offset += sizeof(double);
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__ movsd(spill.AsXmmRegister(), Address(CpuRegister(RSP), offset));
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cfi().Restore(DWARFReg(spill.AsXmmRegister().AsFloatRegister()));
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} else {
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gpr_count++;
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}
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}
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int adjust = static_cast<int>(frame_size) - (gpr_count * kFramePointerSize) - kFramePointerSize;
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__ addq(CpuRegister(RSP), Immediate(adjust));
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cfi().AdjustCFAOffset(-adjust);
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for (size_t i = 0; i < spill_regs.size(); ++i) {
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x86_64::X86_64ManagedRegister spill = spill_regs[i].AsX86_64();
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if (spill.IsCpuRegister()) {
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__ popq(spill.AsCpuRegister());
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cfi().AdjustCFAOffset(-static_cast<int>(kFramePointerSize));
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cfi().Restore(DWARFReg(spill.AsCpuRegister().AsRegister()));
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}
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}
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__ ret();
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// The CFI should be restored for any code that follows the exit block.
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cfi().RestoreState();
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cfi().DefCFAOffset(frame_size);
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}
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void X86_64JNIMacroAssembler::IncreaseFrameSize(size_t adjust) {
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CHECK_ALIGNED(adjust, kStackAlignment);
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__ addq(CpuRegister(RSP), Immediate(-static_cast<int64_t>(adjust)));
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cfi().AdjustCFAOffset(adjust);
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}
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static void DecreaseFrameSizeImpl(size_t adjust, X86_64Assembler* assembler) {
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CHECK_ALIGNED(adjust, kStackAlignment);
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assembler->addq(CpuRegister(RSP), Immediate(adjust));
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assembler->cfi().AdjustCFAOffset(-adjust);
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}
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void X86_64JNIMacroAssembler::DecreaseFrameSize(size_t adjust) {
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DecreaseFrameSizeImpl(adjust, &asm_);
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}
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void X86_64JNIMacroAssembler::Store(FrameOffset offs, ManagedRegister msrc, size_t size) {
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X86_64ManagedRegister src = msrc.AsX86_64();
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if (src.IsNoRegister()) {
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CHECK_EQ(0u, size);
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} else if (src.IsCpuRegister()) {
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if (size == 4) {
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CHECK_EQ(4u, size);
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__ movl(Address(CpuRegister(RSP), offs), src.AsCpuRegister());
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} else {
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CHECK_EQ(8u, size);
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__ movq(Address(CpuRegister(RSP), offs), src.AsCpuRegister());
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}
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} else if (src.IsRegisterPair()) {
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CHECK_EQ(0u, size);
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__ movq(Address(CpuRegister(RSP), offs), src.AsRegisterPairLow());
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__ movq(Address(CpuRegister(RSP), FrameOffset(offs.Int32Value()+4)),
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src.AsRegisterPairHigh());
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} else if (src.IsX87Register()) {
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if (size == 4) {
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__ fstps(Address(CpuRegister(RSP), offs));
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} else {
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__ fstpl(Address(CpuRegister(RSP), offs));
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}
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} else {
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CHECK(src.IsXmmRegister());
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if (size == 4) {
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__ movss(Address(CpuRegister(RSP), offs), src.AsXmmRegister());
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} else {
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__ movsd(Address(CpuRegister(RSP), offs), src.AsXmmRegister());
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}
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}
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}
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void X86_64JNIMacroAssembler::StoreRef(FrameOffset dest, ManagedRegister msrc) {
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X86_64ManagedRegister src = msrc.AsX86_64();
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CHECK(src.IsCpuRegister());
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__ movl(Address(CpuRegister(RSP), dest), src.AsCpuRegister());
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}
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void X86_64JNIMacroAssembler::StoreRawPtr(FrameOffset dest, ManagedRegister msrc) {
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X86_64ManagedRegister src = msrc.AsX86_64();
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CHECK(src.IsCpuRegister());
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__ movq(Address(CpuRegister(RSP), dest), src.AsCpuRegister());
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}
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void X86_64JNIMacroAssembler::StoreImmediateToFrame(FrameOffset dest,
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uint32_t imm,
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ManagedRegister) {
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__ movl(Address(CpuRegister(RSP), dest), Immediate(imm)); // TODO(64) movq?
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}
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void X86_64JNIMacroAssembler::StoreStackOffsetToThread(ThreadOffset64 thr_offs,
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FrameOffset fr_offs,
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ManagedRegister mscratch) {
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X86_64ManagedRegister scratch = mscratch.AsX86_64();
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CHECK(scratch.IsCpuRegister());
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__ leaq(scratch.AsCpuRegister(), Address(CpuRegister(RSP), fr_offs));
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__ gs()->movq(Address::Absolute(thr_offs, true), scratch.AsCpuRegister());
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}
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void X86_64JNIMacroAssembler::StoreStackPointerToThread(ThreadOffset64 thr_offs) {
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__ gs()->movq(Address::Absolute(thr_offs, true), CpuRegister(RSP));
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}
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void X86_64JNIMacroAssembler::StoreSpanning(FrameOffset /*dst*/,
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ManagedRegister /*src*/,
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FrameOffset /*in_off*/,
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ManagedRegister /*scratch*/) {
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UNIMPLEMENTED(FATAL); // this case only currently exists for ARM
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}
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void X86_64JNIMacroAssembler::Load(ManagedRegister mdest, FrameOffset src, size_t size) {
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X86_64ManagedRegister dest = mdest.AsX86_64();
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if (dest.IsNoRegister()) {
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CHECK_EQ(0u, size);
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} else if (dest.IsCpuRegister()) {
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if (size == 4) {
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CHECK_EQ(4u, size);
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__ movl(dest.AsCpuRegister(), Address(CpuRegister(RSP), src));
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} else {
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CHECK_EQ(8u, size);
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__ movq(dest.AsCpuRegister(), Address(CpuRegister(RSP), src));
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}
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} else if (dest.IsRegisterPair()) {
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CHECK_EQ(0u, size);
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__ movq(dest.AsRegisterPairLow(), Address(CpuRegister(RSP), src));
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__ movq(dest.AsRegisterPairHigh(), Address(CpuRegister(RSP), FrameOffset(src.Int32Value()+4)));
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} else if (dest.IsX87Register()) {
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if (size == 4) {
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__ flds(Address(CpuRegister(RSP), src));
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} else {
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__ fldl(Address(CpuRegister(RSP), src));
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}
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} else {
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CHECK(dest.IsXmmRegister());
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if (size == 4) {
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__ movss(dest.AsXmmRegister(), Address(CpuRegister(RSP), src));
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} else {
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__ movsd(dest.AsXmmRegister(), Address(CpuRegister(RSP), src));
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}
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}
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}
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void X86_64JNIMacroAssembler::LoadFromThread(ManagedRegister mdest,
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ThreadOffset64 src, size_t size) {
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X86_64ManagedRegister dest = mdest.AsX86_64();
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if (dest.IsNoRegister()) {
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CHECK_EQ(0u, size);
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} else if (dest.IsCpuRegister()) {
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if (size == 1u) {
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__ gs()->movzxb(dest.AsCpuRegister(), Address::Absolute(src, true));
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} else {
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CHECK_EQ(4u, size);
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__ gs()->movl(dest.AsCpuRegister(), Address::Absolute(src, true));
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}
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} else if (dest.IsRegisterPair()) {
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CHECK_EQ(8u, size);
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__ gs()->movq(dest.AsRegisterPairLow(), Address::Absolute(src, true));
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} else if (dest.IsX87Register()) {
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if (size == 4) {
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__ gs()->flds(Address::Absolute(src, true));
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} else {
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__ gs()->fldl(Address::Absolute(src, true));
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}
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} else {
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CHECK(dest.IsXmmRegister());
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if (size == 4) {
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__ gs()->movss(dest.AsXmmRegister(), Address::Absolute(src, true));
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} else {
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__ gs()->movsd(dest.AsXmmRegister(), Address::Absolute(src, true));
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}
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}
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}
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void X86_64JNIMacroAssembler::LoadRef(ManagedRegister mdest, FrameOffset src) {
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X86_64ManagedRegister dest = mdest.AsX86_64();
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CHECK(dest.IsCpuRegister());
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__ movq(dest.AsCpuRegister(), Address(CpuRegister(RSP), src));
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}
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void X86_64JNIMacroAssembler::LoadRef(ManagedRegister mdest,
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ManagedRegister mbase,
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MemberOffset offs,
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bool unpoison_reference) {
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X86_64ManagedRegister base = mbase.AsX86_64();
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X86_64ManagedRegister dest = mdest.AsX86_64();
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CHECK(base.IsCpuRegister());
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CHECK(dest.IsCpuRegister());
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__ movl(dest.AsCpuRegister(), Address(base.AsCpuRegister(), offs));
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if (unpoison_reference) {
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__ MaybeUnpoisonHeapReference(dest.AsCpuRegister());
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}
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}
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void X86_64JNIMacroAssembler::LoadRawPtr(ManagedRegister mdest,
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ManagedRegister mbase,
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Offset offs) {
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X86_64ManagedRegister base = mbase.AsX86_64();
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X86_64ManagedRegister dest = mdest.AsX86_64();
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CHECK(base.IsCpuRegister());
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CHECK(dest.IsCpuRegister());
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__ movq(dest.AsCpuRegister(), Address(base.AsCpuRegister(), offs));
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}
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void X86_64JNIMacroAssembler::LoadRawPtrFromThread(ManagedRegister mdest, ThreadOffset64 offs) {
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X86_64ManagedRegister dest = mdest.AsX86_64();
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CHECK(dest.IsCpuRegister());
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__ gs()->movq(dest.AsCpuRegister(), Address::Absolute(offs, true));
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}
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void X86_64JNIMacroAssembler::SignExtend(ManagedRegister mreg, size_t size) {
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X86_64ManagedRegister reg = mreg.AsX86_64();
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CHECK(size == 1 || size == 2) << size;
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CHECK(reg.IsCpuRegister()) << reg;
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if (size == 1) {
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__ movsxb(reg.AsCpuRegister(), reg.AsCpuRegister());
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} else {
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__ movsxw(reg.AsCpuRegister(), reg.AsCpuRegister());
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}
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}
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void X86_64JNIMacroAssembler::ZeroExtend(ManagedRegister mreg, size_t size) {
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X86_64ManagedRegister reg = mreg.AsX86_64();
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CHECK(size == 1 || size == 2) << size;
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CHECK(reg.IsCpuRegister()) << reg;
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if (size == 1) {
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__ movzxb(reg.AsCpuRegister(), reg.AsCpuRegister());
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} else {
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__ movzxw(reg.AsCpuRegister(), reg.AsCpuRegister());
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}
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}
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void X86_64JNIMacroAssembler::Move(ManagedRegister mdest, ManagedRegister msrc, size_t size) {
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X86_64ManagedRegister dest = mdest.AsX86_64();
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X86_64ManagedRegister src = msrc.AsX86_64();
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if (!dest.Equals(src)) {
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if (dest.IsCpuRegister() && src.IsCpuRegister()) {
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__ movq(dest.AsCpuRegister(), src.AsCpuRegister());
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} else if (src.IsX87Register() && dest.IsXmmRegister()) {
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// Pass via stack and pop X87 register
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__ subl(CpuRegister(RSP), Immediate(16));
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if (size == 4) {
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CHECK_EQ(src.AsX87Register(), ST0);
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__ fstps(Address(CpuRegister(RSP), 0));
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__ movss(dest.AsXmmRegister(), Address(CpuRegister(RSP), 0));
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} else {
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CHECK_EQ(src.AsX87Register(), ST0);
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__ fstpl(Address(CpuRegister(RSP), 0));
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__ movsd(dest.AsXmmRegister(), Address(CpuRegister(RSP), 0));
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}
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__ addq(CpuRegister(RSP), Immediate(16));
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} else {
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// TODO: x87, SSE
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UNIMPLEMENTED(FATAL) << ": Move " << dest << ", " << src;
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}
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}
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}
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void X86_64JNIMacroAssembler::CopyRef(FrameOffset dest, FrameOffset src, ManagedRegister mscratch) {
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X86_64ManagedRegister scratch = mscratch.AsX86_64();
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CHECK(scratch.IsCpuRegister());
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__ movl(scratch.AsCpuRegister(), Address(CpuRegister(RSP), src));
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__ movl(Address(CpuRegister(RSP), dest), scratch.AsCpuRegister());
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}
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void X86_64JNIMacroAssembler::CopyRawPtrFromThread(FrameOffset fr_offs,
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ThreadOffset64 thr_offs,
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ManagedRegister mscratch) {
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X86_64ManagedRegister scratch = mscratch.AsX86_64();
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CHECK(scratch.IsCpuRegister());
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__ gs()->movq(scratch.AsCpuRegister(), Address::Absolute(thr_offs, true));
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Store(fr_offs, scratch, 8);
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}
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void X86_64JNIMacroAssembler::CopyRawPtrToThread(ThreadOffset64 thr_offs,
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FrameOffset fr_offs,
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ManagedRegister mscratch) {
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X86_64ManagedRegister scratch = mscratch.AsX86_64();
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CHECK(scratch.IsCpuRegister());
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Load(scratch, fr_offs, 8);
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__ gs()->movq(Address::Absolute(thr_offs, true), scratch.AsCpuRegister());
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}
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void X86_64JNIMacroAssembler::Copy(FrameOffset dest,
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FrameOffset src,
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ManagedRegister mscratch,
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size_t size) {
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X86_64ManagedRegister scratch = mscratch.AsX86_64();
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if (scratch.IsCpuRegister() && size == 8) {
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Load(scratch, src, 4);
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Store(dest, scratch, 4);
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Load(scratch, FrameOffset(src.Int32Value() + 4), 4);
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Store(FrameOffset(dest.Int32Value() + 4), scratch, 4);
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} else {
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Load(scratch, src, size);
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Store(dest, scratch, size);
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}
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}
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void X86_64JNIMacroAssembler::Copy(FrameOffset /*dst*/,
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ManagedRegister /*src_base*/,
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Offset /*src_offset*/,
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ManagedRegister /*scratch*/,
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size_t /*size*/) {
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UNIMPLEMENTED(FATAL);
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}
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void X86_64JNIMacroAssembler::Copy(ManagedRegister dest_base,
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Offset dest_offset,
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FrameOffset src,
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ManagedRegister scratch,
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size_t size) {
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CHECK(scratch.IsNoRegister());
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CHECK_EQ(size, 4u);
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__ pushq(Address(CpuRegister(RSP), src));
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__ popq(Address(dest_base.AsX86_64().AsCpuRegister(), dest_offset));
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}
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void X86_64JNIMacroAssembler::Copy(FrameOffset dest,
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FrameOffset src_base,
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Offset src_offset,
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ManagedRegister mscratch,
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size_t size) {
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CpuRegister scratch = mscratch.AsX86_64().AsCpuRegister();
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CHECK_EQ(size, 4u);
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__ movq(scratch, Address(CpuRegister(RSP), src_base));
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__ movq(scratch, Address(scratch, src_offset));
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__ movq(Address(CpuRegister(RSP), dest), scratch);
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}
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void X86_64JNIMacroAssembler::Copy(ManagedRegister dest,
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Offset dest_offset,
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ManagedRegister src,
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Offset src_offset,
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ManagedRegister scratch,
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size_t size) {
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CHECK_EQ(size, 4u);
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CHECK(scratch.IsNoRegister());
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__ pushq(Address(src.AsX86_64().AsCpuRegister(), src_offset));
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__ popq(Address(dest.AsX86_64().AsCpuRegister(), dest_offset));
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}
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void X86_64JNIMacroAssembler::Copy(FrameOffset dest,
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Offset dest_offset,
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FrameOffset src,
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Offset src_offset,
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ManagedRegister mscratch,
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size_t size) {
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CpuRegister scratch = mscratch.AsX86_64().AsCpuRegister();
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CHECK_EQ(size, 4u);
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CHECK_EQ(dest.Int32Value(), src.Int32Value());
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__ movq(scratch, Address(CpuRegister(RSP), src));
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__ pushq(Address(scratch, src_offset));
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__ popq(Address(scratch, dest_offset));
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}
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void X86_64JNIMacroAssembler::MemoryBarrier(ManagedRegister) {
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__ mfence();
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}
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void X86_64JNIMacroAssembler::CreateHandleScopeEntry(ManagedRegister mout_reg,
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FrameOffset handle_scope_offset,
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ManagedRegister min_reg,
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bool null_allowed) {
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X86_64ManagedRegister out_reg = mout_reg.AsX86_64();
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X86_64ManagedRegister in_reg = min_reg.AsX86_64();
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if (in_reg.IsNoRegister()) { // TODO(64): && null_allowed
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// Use out_reg as indicator of null.
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in_reg = out_reg;
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// TODO: movzwl
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__ movl(in_reg.AsCpuRegister(), Address(CpuRegister(RSP), handle_scope_offset));
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}
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CHECK(in_reg.IsCpuRegister());
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CHECK(out_reg.IsCpuRegister());
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VerifyObject(in_reg, null_allowed);
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if (null_allowed) {
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Label null_arg;
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if (!out_reg.Equals(in_reg)) {
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__ xorl(out_reg.AsCpuRegister(), out_reg.AsCpuRegister());
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}
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__ testl(in_reg.AsCpuRegister(), in_reg.AsCpuRegister());
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__ j(kZero, &null_arg);
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__ leaq(out_reg.AsCpuRegister(), Address(CpuRegister(RSP), handle_scope_offset));
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__ Bind(&null_arg);
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} else {
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__ leaq(out_reg.AsCpuRegister(), Address(CpuRegister(RSP), handle_scope_offset));
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}
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}
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void X86_64JNIMacroAssembler::CreateHandleScopeEntry(FrameOffset out_off,
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FrameOffset handle_scope_offset,
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ManagedRegister mscratch,
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bool null_allowed) {
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X86_64ManagedRegister scratch = mscratch.AsX86_64();
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CHECK(scratch.IsCpuRegister());
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if (null_allowed) {
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Label null_arg;
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__ movl(scratch.AsCpuRegister(), Address(CpuRegister(RSP), handle_scope_offset));
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__ testl(scratch.AsCpuRegister(), scratch.AsCpuRegister());
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__ j(kZero, &null_arg);
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__ leaq(scratch.AsCpuRegister(), Address(CpuRegister(RSP), handle_scope_offset));
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__ Bind(&null_arg);
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} else {
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__ leaq(scratch.AsCpuRegister(), Address(CpuRegister(RSP), handle_scope_offset));
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}
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Store(out_off, scratch, 8);
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}
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// Given a handle scope entry, load the associated reference.
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void X86_64JNIMacroAssembler::LoadReferenceFromHandleScope(ManagedRegister mout_reg,
|
ManagedRegister min_reg) {
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X86_64ManagedRegister out_reg = mout_reg.AsX86_64();
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X86_64ManagedRegister in_reg = min_reg.AsX86_64();
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CHECK(out_reg.IsCpuRegister());
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CHECK(in_reg.IsCpuRegister());
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Label null_arg;
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if (!out_reg.Equals(in_reg)) {
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__ xorl(out_reg.AsCpuRegister(), out_reg.AsCpuRegister());
|
}
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__ testl(in_reg.AsCpuRegister(), in_reg.AsCpuRegister());
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__ j(kZero, &null_arg);
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__ movq(out_reg.AsCpuRegister(), Address(in_reg.AsCpuRegister(), 0));
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__ Bind(&null_arg);
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}
|
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void X86_64JNIMacroAssembler::VerifyObject(ManagedRegister /*src*/, bool /*could_be_null*/) {
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// TODO: not validating references
|
}
|
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void X86_64JNIMacroAssembler::VerifyObject(FrameOffset /*src*/, bool /*could_be_null*/) {
|
// TODO: not validating references
|
}
|
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void X86_64JNIMacroAssembler::Call(ManagedRegister mbase, Offset offset, ManagedRegister) {
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X86_64ManagedRegister base = mbase.AsX86_64();
|
CHECK(base.IsCpuRegister());
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__ call(Address(base.AsCpuRegister(), offset.Int32Value()));
|
// TODO: place reference map on call
|
}
|
|
void X86_64JNIMacroAssembler::Call(FrameOffset base, Offset offset, ManagedRegister mscratch) {
|
CpuRegister scratch = mscratch.AsX86_64().AsCpuRegister();
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__ movq(scratch, Address(CpuRegister(RSP), base));
|
__ call(Address(scratch, offset));
|
}
|
|
void X86_64JNIMacroAssembler::CallFromThread(ThreadOffset64 offset, ManagedRegister /*mscratch*/) {
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__ gs()->call(Address::Absolute(offset, true));
|
}
|
|
void X86_64JNIMacroAssembler::GetCurrentThread(ManagedRegister tr) {
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__ gs()->movq(tr.AsX86_64().AsCpuRegister(),
|
Address::Absolute(Thread::SelfOffset<kX86_64PointerSize>(), true));
|
}
|
|
void X86_64JNIMacroAssembler::GetCurrentThread(FrameOffset offset, ManagedRegister mscratch) {
|
X86_64ManagedRegister scratch = mscratch.AsX86_64();
|
__ gs()->movq(scratch.AsCpuRegister(),
|
Address::Absolute(Thread::SelfOffset<kX86_64PointerSize>(), true));
|
__ movq(Address(CpuRegister(RSP), offset), scratch.AsCpuRegister());
|
}
|
|
// Slowpath entered when Thread::Current()->_exception is non-null
|
class X86_64ExceptionSlowPath final : public SlowPath {
|
public:
|
explicit X86_64ExceptionSlowPath(size_t stack_adjust) : stack_adjust_(stack_adjust) {}
|
void Emit(Assembler *sp_asm) override;
|
private:
|
const size_t stack_adjust_;
|
};
|
|
void X86_64JNIMacroAssembler::ExceptionPoll(ManagedRegister /*scratch*/, size_t stack_adjust) {
|
X86_64ExceptionSlowPath* slow = new (__ GetAllocator()) X86_64ExceptionSlowPath(stack_adjust);
|
__ GetBuffer()->EnqueueSlowPath(slow);
|
__ gs()->cmpl(Address::Absolute(Thread::ExceptionOffset<kX86_64PointerSize>(), true),
|
Immediate(0));
|
__ j(kNotEqual, slow->Entry());
|
}
|
|
std::unique_ptr<JNIMacroLabel> X86_64JNIMacroAssembler::CreateLabel() {
|
return std::unique_ptr<JNIMacroLabel>(new X86_64JNIMacroLabel());
|
}
|
|
void X86_64JNIMacroAssembler::Jump(JNIMacroLabel* label) {
|
CHECK(label != nullptr);
|
__ jmp(X86_64JNIMacroLabel::Cast(label)->AsX86_64());
|
}
|
|
void X86_64JNIMacroAssembler::Jump(JNIMacroLabel* label,
|
JNIMacroUnaryCondition condition,
|
ManagedRegister test) {
|
CHECK(label != nullptr);
|
|
art::x86_64::Condition x86_64_cond;
|
switch (condition) {
|
case JNIMacroUnaryCondition::kZero:
|
x86_64_cond = art::x86_64::kZero;
|
break;
|
case JNIMacroUnaryCondition::kNotZero:
|
x86_64_cond = art::x86_64::kNotZero;
|
break;
|
default:
|
LOG(FATAL) << "Not implemented condition: " << static_cast<int>(condition);
|
UNREACHABLE();
|
}
|
|
// TEST reg, reg
|
// Jcc <Offset>
|
__ testq(test.AsX86_64().AsCpuRegister(), test.AsX86_64().AsCpuRegister());
|
__ j(x86_64_cond, X86_64JNIMacroLabel::Cast(label)->AsX86_64());
|
}
|
|
void X86_64JNIMacroAssembler::Bind(JNIMacroLabel* label) {
|
CHECK(label != nullptr);
|
__ Bind(X86_64JNIMacroLabel::Cast(label)->AsX86_64());
|
}
|
|
#undef __
|
|
void X86_64ExceptionSlowPath::Emit(Assembler *sasm) {
|
X86_64Assembler* sp_asm = down_cast<X86_64Assembler*>(sasm);
|
#define __ sp_asm->
|
__ Bind(&entry_);
|
// Note: the return value is dead
|
if (stack_adjust_ != 0) { // Fix up the frame.
|
DecreaseFrameSizeImpl(stack_adjust_, sp_asm);
|
}
|
// Pass exception as argument in RDI
|
__ gs()->movq(CpuRegister(RDI),
|
Address::Absolute(Thread::ExceptionOffset<kX86_64PointerSize>(), true));
|
__ gs()->call(
|
Address::Absolute(QUICK_ENTRYPOINT_OFFSET(kX86_64PointerSize, pDeliverException), true));
|
// this call should never return
|
__ int3();
|
#undef __
|
}
|
|
} // namespace x86_64
|
} // namespace art
|
