/*
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* Copyright (C) 2017 The Android Open Source Project
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#include "managed_register_mips64.h"
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#include "base/globals.h"
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#include "gtest/gtest.h"
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namespace art {
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namespace mips64 {
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TEST(Mips64ManagedRegister, NoRegister) {
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Mips64ManagedRegister reg = ManagedRegister::NoRegister().AsMips64();
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EXPECT_TRUE(reg.IsNoRegister());
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EXPECT_FALSE(reg.Overlaps(reg));
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}
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TEST(Mips64ManagedRegister, GpuRegister) {
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Mips64ManagedRegister reg = Mips64ManagedRegister::FromGpuRegister(ZERO);
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EXPECT_FALSE(reg.IsNoRegister());
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EXPECT_TRUE(reg.IsGpuRegister());
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EXPECT_FALSE(reg.IsFpuRegister());
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EXPECT_FALSE(reg.IsVectorRegister());
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EXPECT_EQ(ZERO, reg.AsGpuRegister());
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reg = Mips64ManagedRegister::FromGpuRegister(AT);
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EXPECT_FALSE(reg.IsNoRegister());
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EXPECT_TRUE(reg.IsGpuRegister());
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EXPECT_FALSE(reg.IsFpuRegister());
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EXPECT_FALSE(reg.IsVectorRegister());
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EXPECT_EQ(AT, reg.AsGpuRegister());
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reg = Mips64ManagedRegister::FromGpuRegister(V0);
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EXPECT_FALSE(reg.IsNoRegister());
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EXPECT_TRUE(reg.IsGpuRegister());
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EXPECT_FALSE(reg.IsFpuRegister());
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EXPECT_FALSE(reg.IsVectorRegister());
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EXPECT_EQ(V0, reg.AsGpuRegister());
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reg = Mips64ManagedRegister::FromGpuRegister(A0);
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EXPECT_FALSE(reg.IsNoRegister());
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EXPECT_TRUE(reg.IsGpuRegister());
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EXPECT_FALSE(reg.IsFpuRegister());
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EXPECT_FALSE(reg.IsVectorRegister());
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EXPECT_EQ(A0, reg.AsGpuRegister());
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reg = Mips64ManagedRegister::FromGpuRegister(A7);
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EXPECT_FALSE(reg.IsNoRegister());
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EXPECT_TRUE(reg.IsGpuRegister());
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EXPECT_FALSE(reg.IsFpuRegister());
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EXPECT_FALSE(reg.IsVectorRegister());
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EXPECT_EQ(A7, reg.AsGpuRegister());
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reg = Mips64ManagedRegister::FromGpuRegister(T0);
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EXPECT_FALSE(reg.IsNoRegister());
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EXPECT_TRUE(reg.IsGpuRegister());
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EXPECT_FALSE(reg.IsFpuRegister());
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EXPECT_FALSE(reg.IsVectorRegister());
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EXPECT_EQ(T0, reg.AsGpuRegister());
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reg = Mips64ManagedRegister::FromGpuRegister(T3);
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EXPECT_FALSE(reg.IsNoRegister());
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EXPECT_TRUE(reg.IsGpuRegister());
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EXPECT_FALSE(reg.IsFpuRegister());
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EXPECT_FALSE(reg.IsVectorRegister());
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EXPECT_EQ(T3, reg.AsGpuRegister());
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reg = Mips64ManagedRegister::FromGpuRegister(S0);
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EXPECT_FALSE(reg.IsNoRegister());
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EXPECT_TRUE(reg.IsGpuRegister());
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EXPECT_FALSE(reg.IsFpuRegister());
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EXPECT_FALSE(reg.IsVectorRegister());
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EXPECT_EQ(S0, reg.AsGpuRegister());
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reg = Mips64ManagedRegister::FromGpuRegister(GP);
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EXPECT_FALSE(reg.IsNoRegister());
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EXPECT_TRUE(reg.IsGpuRegister());
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EXPECT_FALSE(reg.IsFpuRegister());
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EXPECT_FALSE(reg.IsVectorRegister());
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EXPECT_EQ(GP, reg.AsGpuRegister());
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reg = Mips64ManagedRegister::FromGpuRegister(SP);
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EXPECT_FALSE(reg.IsNoRegister());
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EXPECT_TRUE(reg.IsGpuRegister());
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EXPECT_FALSE(reg.IsFpuRegister());
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EXPECT_FALSE(reg.IsVectorRegister());
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EXPECT_EQ(SP, reg.AsGpuRegister());
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reg = Mips64ManagedRegister::FromGpuRegister(RA);
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EXPECT_FALSE(reg.IsNoRegister());
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EXPECT_TRUE(reg.IsGpuRegister());
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EXPECT_FALSE(reg.IsFpuRegister());
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EXPECT_FALSE(reg.IsVectorRegister());
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EXPECT_EQ(RA, reg.AsGpuRegister());
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}
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TEST(Mips64ManagedRegister, FpuRegister) {
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Mips64ManagedRegister reg = Mips64ManagedRegister::FromFpuRegister(F0);
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Mips64ManagedRegister vreg = Mips64ManagedRegister::FromVectorRegister(W0);
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EXPECT_FALSE(reg.IsNoRegister());
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EXPECT_FALSE(reg.IsGpuRegister());
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EXPECT_TRUE(reg.IsFpuRegister());
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EXPECT_FALSE(reg.IsVectorRegister());
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EXPECT_TRUE(reg.Overlaps(vreg));
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EXPECT_EQ(F0, reg.AsFpuRegister());
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EXPECT_EQ(W0, reg.AsOverlappingVectorRegister());
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EXPECT_TRUE(reg.Equals(Mips64ManagedRegister::FromFpuRegister(F0)));
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reg = Mips64ManagedRegister::FromFpuRegister(F1);
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vreg = Mips64ManagedRegister::FromVectorRegister(W1);
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EXPECT_FALSE(reg.IsNoRegister());
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EXPECT_FALSE(reg.IsGpuRegister());
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EXPECT_TRUE(reg.IsFpuRegister());
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EXPECT_FALSE(reg.IsVectorRegister());
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EXPECT_TRUE(reg.Overlaps(vreg));
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EXPECT_EQ(F1, reg.AsFpuRegister());
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EXPECT_EQ(W1, reg.AsOverlappingVectorRegister());
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EXPECT_TRUE(reg.Equals(Mips64ManagedRegister::FromFpuRegister(F1)));
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reg = Mips64ManagedRegister::FromFpuRegister(F20);
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vreg = Mips64ManagedRegister::FromVectorRegister(W20);
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EXPECT_FALSE(reg.IsNoRegister());
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EXPECT_FALSE(reg.IsGpuRegister());
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EXPECT_TRUE(reg.IsFpuRegister());
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EXPECT_FALSE(reg.IsVectorRegister());
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EXPECT_TRUE(reg.Overlaps(vreg));
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EXPECT_EQ(F20, reg.AsFpuRegister());
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EXPECT_EQ(W20, reg.AsOverlappingVectorRegister());
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EXPECT_TRUE(reg.Equals(Mips64ManagedRegister::FromFpuRegister(F20)));
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reg = Mips64ManagedRegister::FromFpuRegister(F31);
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vreg = Mips64ManagedRegister::FromVectorRegister(W31);
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EXPECT_FALSE(reg.IsNoRegister());
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EXPECT_FALSE(reg.IsGpuRegister());
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EXPECT_TRUE(reg.IsFpuRegister());
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EXPECT_FALSE(reg.IsVectorRegister());
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EXPECT_TRUE(reg.Overlaps(vreg));
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EXPECT_EQ(F31, reg.AsFpuRegister());
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EXPECT_EQ(W31, reg.AsOverlappingVectorRegister());
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EXPECT_TRUE(reg.Equals(Mips64ManagedRegister::FromFpuRegister(F31)));
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}
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TEST(Mips64ManagedRegister, VectorRegister) {
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Mips64ManagedRegister reg = Mips64ManagedRegister::FromVectorRegister(W0);
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Mips64ManagedRegister freg = Mips64ManagedRegister::FromFpuRegister(F0);
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EXPECT_FALSE(reg.IsNoRegister());
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EXPECT_FALSE(reg.IsGpuRegister());
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EXPECT_FALSE(reg.IsFpuRegister());
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EXPECT_TRUE(reg.IsVectorRegister());
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EXPECT_TRUE(reg.Overlaps(freg));
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EXPECT_EQ(W0, reg.AsVectorRegister());
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EXPECT_EQ(F0, reg.AsOverlappingFpuRegister());
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EXPECT_TRUE(reg.Equals(Mips64ManagedRegister::FromVectorRegister(W0)));
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reg = Mips64ManagedRegister::FromVectorRegister(W2);
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freg = Mips64ManagedRegister::FromFpuRegister(F2);
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EXPECT_FALSE(reg.IsNoRegister());
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EXPECT_FALSE(reg.IsGpuRegister());
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EXPECT_FALSE(reg.IsFpuRegister());
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EXPECT_TRUE(reg.IsVectorRegister());
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EXPECT_TRUE(reg.Overlaps(freg));
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EXPECT_EQ(W2, reg.AsVectorRegister());
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EXPECT_EQ(F2, reg.AsOverlappingFpuRegister());
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EXPECT_TRUE(reg.Equals(Mips64ManagedRegister::FromVectorRegister(W2)));
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reg = Mips64ManagedRegister::FromVectorRegister(W13);
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freg = Mips64ManagedRegister::FromFpuRegister(F13);
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EXPECT_FALSE(reg.IsNoRegister());
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EXPECT_FALSE(reg.IsGpuRegister());
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EXPECT_FALSE(reg.IsFpuRegister());
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EXPECT_TRUE(reg.IsVectorRegister());
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EXPECT_TRUE(reg.Overlaps(freg));
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EXPECT_EQ(W13, reg.AsVectorRegister());
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EXPECT_EQ(F13, reg.AsOverlappingFpuRegister());
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EXPECT_TRUE(reg.Equals(Mips64ManagedRegister::FromVectorRegister(W13)));
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reg = Mips64ManagedRegister::FromVectorRegister(W29);
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freg = Mips64ManagedRegister::FromFpuRegister(F29);
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EXPECT_FALSE(reg.IsNoRegister());
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EXPECT_FALSE(reg.IsGpuRegister());
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EXPECT_FALSE(reg.IsFpuRegister());
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EXPECT_TRUE(reg.IsVectorRegister());
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EXPECT_TRUE(reg.Overlaps(freg));
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EXPECT_EQ(W29, reg.AsVectorRegister());
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EXPECT_EQ(F29, reg.AsOverlappingFpuRegister());
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EXPECT_TRUE(reg.Equals(Mips64ManagedRegister::FromVectorRegister(W29)));
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}
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TEST(Mips64ManagedRegister, Equals) {
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ManagedRegister no_reg = ManagedRegister::NoRegister();
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EXPECT_TRUE(no_reg.Equals(Mips64ManagedRegister::NoRegister()));
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EXPECT_FALSE(no_reg.Equals(Mips64ManagedRegister::FromGpuRegister(ZERO)));
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EXPECT_FALSE(no_reg.Equals(Mips64ManagedRegister::FromGpuRegister(A1)));
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EXPECT_FALSE(no_reg.Equals(Mips64ManagedRegister::FromGpuRegister(S2)));
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EXPECT_FALSE(no_reg.Equals(Mips64ManagedRegister::FromFpuRegister(F0)));
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EXPECT_FALSE(no_reg.Equals(Mips64ManagedRegister::FromVectorRegister(W0)));
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Mips64ManagedRegister reg_ZERO = Mips64ManagedRegister::FromGpuRegister(ZERO);
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EXPECT_FALSE(reg_ZERO.Equals(Mips64ManagedRegister::NoRegister()));
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EXPECT_TRUE(reg_ZERO.Equals(Mips64ManagedRegister::FromGpuRegister(ZERO)));
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EXPECT_FALSE(reg_ZERO.Equals(Mips64ManagedRegister::FromGpuRegister(A1)));
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EXPECT_FALSE(reg_ZERO.Equals(Mips64ManagedRegister::FromGpuRegister(S2)));
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EXPECT_FALSE(reg_ZERO.Equals(Mips64ManagedRegister::FromFpuRegister(F0)));
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EXPECT_FALSE(reg_ZERO.Equals(Mips64ManagedRegister::FromVectorRegister(W0)));
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Mips64ManagedRegister reg_A1 = Mips64ManagedRegister::FromGpuRegister(A1);
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EXPECT_FALSE(reg_A1.Equals(Mips64ManagedRegister::NoRegister()));
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EXPECT_FALSE(reg_A1.Equals(Mips64ManagedRegister::FromGpuRegister(ZERO)));
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EXPECT_FALSE(reg_A1.Equals(Mips64ManagedRegister::FromGpuRegister(A0)));
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EXPECT_TRUE(reg_A1.Equals(Mips64ManagedRegister::FromGpuRegister(A1)));
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EXPECT_FALSE(reg_A1.Equals(Mips64ManagedRegister::FromGpuRegister(S2)));
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EXPECT_FALSE(reg_A1.Equals(Mips64ManagedRegister::FromFpuRegister(F0)));
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EXPECT_FALSE(reg_A1.Equals(Mips64ManagedRegister::FromVectorRegister(W0)));
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Mips64ManagedRegister reg_S2 = Mips64ManagedRegister::FromGpuRegister(S2);
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EXPECT_FALSE(reg_S2.Equals(Mips64ManagedRegister::NoRegister()));
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EXPECT_FALSE(reg_S2.Equals(Mips64ManagedRegister::FromGpuRegister(ZERO)));
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EXPECT_FALSE(reg_S2.Equals(Mips64ManagedRegister::FromGpuRegister(A1)));
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EXPECT_FALSE(reg_S2.Equals(Mips64ManagedRegister::FromGpuRegister(S1)));
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EXPECT_TRUE(reg_S2.Equals(Mips64ManagedRegister::FromGpuRegister(S2)));
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EXPECT_FALSE(reg_S2.Equals(Mips64ManagedRegister::FromFpuRegister(F0)));
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EXPECT_FALSE(reg_S2.Equals(Mips64ManagedRegister::FromVectorRegister(W0)));
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Mips64ManagedRegister reg_F0 = Mips64ManagedRegister::FromFpuRegister(F0);
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EXPECT_FALSE(reg_F0.Equals(Mips64ManagedRegister::NoRegister()));
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EXPECT_FALSE(reg_F0.Equals(Mips64ManagedRegister::FromGpuRegister(ZERO)));
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EXPECT_FALSE(reg_F0.Equals(Mips64ManagedRegister::FromGpuRegister(A1)));
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EXPECT_FALSE(reg_F0.Equals(Mips64ManagedRegister::FromGpuRegister(S2)));
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EXPECT_TRUE(reg_F0.Equals(Mips64ManagedRegister::FromFpuRegister(F0)));
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EXPECT_FALSE(reg_F0.Equals(Mips64ManagedRegister::FromFpuRegister(F1)));
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EXPECT_FALSE(reg_F0.Equals(Mips64ManagedRegister::FromFpuRegister(F31)));
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EXPECT_FALSE(reg_F0.Equals(Mips64ManagedRegister::FromVectorRegister(W0)));
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Mips64ManagedRegister reg_F31 = Mips64ManagedRegister::FromFpuRegister(F31);
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EXPECT_FALSE(reg_F31.Equals(Mips64ManagedRegister::NoRegister()));
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EXPECT_FALSE(reg_F31.Equals(Mips64ManagedRegister::FromGpuRegister(ZERO)));
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EXPECT_FALSE(reg_F31.Equals(Mips64ManagedRegister::FromGpuRegister(A1)));
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EXPECT_FALSE(reg_F31.Equals(Mips64ManagedRegister::FromGpuRegister(S2)));
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EXPECT_FALSE(reg_F31.Equals(Mips64ManagedRegister::FromFpuRegister(F0)));
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EXPECT_FALSE(reg_F31.Equals(Mips64ManagedRegister::FromFpuRegister(F1)));
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EXPECT_TRUE(reg_F31.Equals(Mips64ManagedRegister::FromFpuRegister(F31)));
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EXPECT_FALSE(reg_F31.Equals(Mips64ManagedRegister::FromVectorRegister(W0)));
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Mips64ManagedRegister reg_W0 = Mips64ManagedRegister::FromVectorRegister(W0);
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EXPECT_FALSE(reg_W0.Equals(Mips64ManagedRegister::NoRegister()));
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EXPECT_FALSE(reg_W0.Equals(Mips64ManagedRegister::FromGpuRegister(ZERO)));
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EXPECT_FALSE(reg_W0.Equals(Mips64ManagedRegister::FromGpuRegister(A1)));
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EXPECT_FALSE(reg_W0.Equals(Mips64ManagedRegister::FromGpuRegister(S1)));
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EXPECT_FALSE(reg_W0.Equals(Mips64ManagedRegister::FromFpuRegister(F0)));
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EXPECT_TRUE(reg_W0.Equals(Mips64ManagedRegister::FromVectorRegister(W0)));
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EXPECT_FALSE(reg_W0.Equals(Mips64ManagedRegister::FromVectorRegister(W1)));
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EXPECT_FALSE(reg_W0.Equals(Mips64ManagedRegister::FromVectorRegister(W31)));
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Mips64ManagedRegister reg_W31 = Mips64ManagedRegister::FromVectorRegister(W31);
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EXPECT_FALSE(reg_W31.Equals(Mips64ManagedRegister::NoRegister()));
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EXPECT_FALSE(reg_W31.Equals(Mips64ManagedRegister::FromGpuRegister(ZERO)));
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EXPECT_FALSE(reg_W31.Equals(Mips64ManagedRegister::FromGpuRegister(A1)));
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EXPECT_FALSE(reg_W31.Equals(Mips64ManagedRegister::FromGpuRegister(S1)));
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EXPECT_FALSE(reg_W31.Equals(Mips64ManagedRegister::FromFpuRegister(F0)));
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EXPECT_FALSE(reg_W31.Equals(Mips64ManagedRegister::FromVectorRegister(W0)));
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EXPECT_FALSE(reg_W31.Equals(Mips64ManagedRegister::FromVectorRegister(W1)));
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EXPECT_TRUE(reg_W31.Equals(Mips64ManagedRegister::FromVectorRegister(W31)));
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}
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TEST(Mips64ManagedRegister, Overlaps) {
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Mips64ManagedRegister reg = Mips64ManagedRegister::FromFpuRegister(F0);
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Mips64ManagedRegister reg_o = Mips64ManagedRegister::FromVectorRegister(W0);
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EXPECT_TRUE(reg.Overlaps(reg_o));
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EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromGpuRegister(ZERO)));
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EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromGpuRegister(A0)));
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EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromGpuRegister(S0)));
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EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromGpuRegister(RA)));
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EXPECT_EQ(F0, reg_o.AsOverlappingFpuRegister());
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EXPECT_EQ(W0, reg.AsOverlappingVectorRegister());
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EXPECT_TRUE(reg.Overlaps(Mips64ManagedRegister::FromFpuRegister(F0)));
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EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromFpuRegister(F4)));
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EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromFpuRegister(F16)));
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EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromFpuRegister(F31)));
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EXPECT_TRUE(reg.Overlaps(Mips64ManagedRegister::FromVectorRegister(W0)));
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EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromVectorRegister(W4)));
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EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromVectorRegister(W16)));
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EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromVectorRegister(W31)));
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reg = Mips64ManagedRegister::FromFpuRegister(F4);
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reg_o = Mips64ManagedRegister::FromVectorRegister(W4);
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EXPECT_TRUE(reg.Overlaps(reg_o));
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EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromGpuRegister(ZERO)));
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EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromGpuRegister(A0)));
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EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromGpuRegister(S0)));
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EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromGpuRegister(RA)));
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EXPECT_EQ(F4, reg_o.AsOverlappingFpuRegister());
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EXPECT_EQ(W4, reg.AsOverlappingVectorRegister());
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EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromFpuRegister(F0)));
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EXPECT_TRUE(reg.Overlaps(Mips64ManagedRegister::FromFpuRegister(F4)));
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EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromFpuRegister(F16)));
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EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromFpuRegister(F31)));
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EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromVectorRegister(W0)));
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EXPECT_TRUE(reg.Overlaps(Mips64ManagedRegister::FromVectorRegister(W4)));
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EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromVectorRegister(W16)));
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EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromVectorRegister(W31)));
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reg = Mips64ManagedRegister::FromFpuRegister(F16);
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reg_o = Mips64ManagedRegister::FromVectorRegister(W16);
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EXPECT_TRUE(reg.Overlaps(reg_o));
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EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromGpuRegister(ZERO)));
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EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromGpuRegister(A0)));
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EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromGpuRegister(S0)));
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EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromGpuRegister(RA)));
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EXPECT_EQ(F16, reg_o.AsOverlappingFpuRegister());
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EXPECT_EQ(W16, reg.AsOverlappingVectorRegister());
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EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromFpuRegister(F0)));
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EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromFpuRegister(F4)));
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EXPECT_TRUE(reg.Overlaps(Mips64ManagedRegister::FromFpuRegister(F16)));
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EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromFpuRegister(F31)));
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EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromVectorRegister(W0)));
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EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromVectorRegister(W4)));
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EXPECT_TRUE(reg.Overlaps(Mips64ManagedRegister::FromVectorRegister(W16)));
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EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromVectorRegister(W31)));
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reg = Mips64ManagedRegister::FromFpuRegister(F31);
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reg_o = Mips64ManagedRegister::FromVectorRegister(W31);
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EXPECT_TRUE(reg.Overlaps(reg_o));
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EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromGpuRegister(ZERO)));
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EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromGpuRegister(A0)));
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EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromGpuRegister(S0)));
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EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromGpuRegister(RA)));
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EXPECT_EQ(F31, reg_o.AsOverlappingFpuRegister());
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EXPECT_EQ(W31, reg.AsOverlappingVectorRegister());
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EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromFpuRegister(F0)));
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EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromFpuRegister(F4)));
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EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromFpuRegister(F16)));
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EXPECT_TRUE(reg.Overlaps(Mips64ManagedRegister::FromFpuRegister(F31)));
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EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromVectorRegister(W0)));
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EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromVectorRegister(W4)));
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EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromVectorRegister(W16)));
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EXPECT_TRUE(reg.Overlaps(Mips64ManagedRegister::FromVectorRegister(W31)));
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reg = Mips64ManagedRegister::FromVectorRegister(W0);
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reg_o = Mips64ManagedRegister::FromFpuRegister(F0);
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EXPECT_TRUE(reg.Overlaps(reg_o));
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EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromGpuRegister(ZERO)));
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EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromGpuRegister(A0)));
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EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromGpuRegister(S0)));
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EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromGpuRegister(RA)));
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EXPECT_EQ(W0, reg_o.AsOverlappingVectorRegister());
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EXPECT_EQ(F0, reg.AsOverlappingFpuRegister());
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EXPECT_TRUE(reg.Overlaps(Mips64ManagedRegister::FromFpuRegister(F0)));
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EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromFpuRegister(F4)));
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EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromFpuRegister(F16)));
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EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromFpuRegister(F31)));
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EXPECT_TRUE(reg.Overlaps(Mips64ManagedRegister::FromVectorRegister(W0)));
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EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromVectorRegister(W4)));
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EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromVectorRegister(W16)));
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EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromVectorRegister(W31)));
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reg = Mips64ManagedRegister::FromVectorRegister(W4);
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reg_o = Mips64ManagedRegister::FromFpuRegister(F4);
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EXPECT_TRUE(reg.Overlaps(reg_o));
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EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromGpuRegister(ZERO)));
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EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromGpuRegister(A0)));
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EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromGpuRegister(S0)));
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EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromGpuRegister(RA)));
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EXPECT_EQ(W4, reg_o.AsOverlappingVectorRegister());
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EXPECT_EQ(F4, reg.AsOverlappingFpuRegister());
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EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromFpuRegister(F0)));
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EXPECT_TRUE(reg.Overlaps(Mips64ManagedRegister::FromFpuRegister(F4)));
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EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromFpuRegister(F16)));
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EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromFpuRegister(F31)));
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EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromVectorRegister(W0)));
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EXPECT_TRUE(reg.Overlaps(Mips64ManagedRegister::FromVectorRegister(W4)));
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EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromVectorRegister(W16)));
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EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromVectorRegister(W31)));
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reg = Mips64ManagedRegister::FromVectorRegister(W16);
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reg_o = Mips64ManagedRegister::FromFpuRegister(F16);
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EXPECT_TRUE(reg.Overlaps(reg_o));
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EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromGpuRegister(ZERO)));
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EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromGpuRegister(A0)));
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EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromGpuRegister(S0)));
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EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromGpuRegister(RA)));
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EXPECT_EQ(W16, reg_o.AsOverlappingVectorRegister());
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EXPECT_EQ(F16, reg.AsOverlappingFpuRegister());
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EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromFpuRegister(F0)));
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EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromFpuRegister(F4)));
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EXPECT_TRUE(reg.Overlaps(Mips64ManagedRegister::FromFpuRegister(F16)));
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EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromFpuRegister(F31)));
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EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromVectorRegister(W0)));
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EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromVectorRegister(W4)));
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EXPECT_TRUE(reg.Overlaps(Mips64ManagedRegister::FromVectorRegister(W16)));
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EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromVectorRegister(W31)));
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reg = Mips64ManagedRegister::FromVectorRegister(W31);
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reg_o = Mips64ManagedRegister::FromFpuRegister(F31);
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EXPECT_TRUE(reg.Overlaps(reg_o));
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EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromGpuRegister(ZERO)));
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EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromGpuRegister(A0)));
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EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromGpuRegister(S0)));
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EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromGpuRegister(RA)));
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EXPECT_EQ(W31, reg_o.AsOverlappingVectorRegister());
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EXPECT_EQ(F31, reg.AsOverlappingFpuRegister());
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EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromFpuRegister(F0)));
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EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromFpuRegister(F4)));
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EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromFpuRegister(F16)));
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EXPECT_TRUE(reg.Overlaps(Mips64ManagedRegister::FromFpuRegister(F31)));
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EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromVectorRegister(W0)));
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EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromVectorRegister(W4)));
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EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromVectorRegister(W16)));
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EXPECT_TRUE(reg.Overlaps(Mips64ManagedRegister::FromVectorRegister(W31)));
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reg = Mips64ManagedRegister::FromGpuRegister(ZERO);
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EXPECT_TRUE(reg.Overlaps(Mips64ManagedRegister::FromGpuRegister(ZERO)));
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EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromGpuRegister(A0)));
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EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromGpuRegister(S0)));
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EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromGpuRegister(RA)));
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EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromFpuRegister(F0)));
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EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromFpuRegister(F4)));
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EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromFpuRegister(F16)));
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EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromFpuRegister(F31)));
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EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromVectorRegister(W0)));
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EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromVectorRegister(W4)));
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EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromVectorRegister(W16)));
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EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromVectorRegister(W31)));
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reg = Mips64ManagedRegister::FromGpuRegister(A0);
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EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromGpuRegister(ZERO)));
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EXPECT_TRUE(reg.Overlaps(Mips64ManagedRegister::FromGpuRegister(A0)));
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EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromGpuRegister(S0)));
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EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromGpuRegister(RA)));
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EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromFpuRegister(F0)));
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EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromFpuRegister(F4)));
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EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromFpuRegister(F16)));
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EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromFpuRegister(F31)));
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EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromVectorRegister(W0)));
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EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromVectorRegister(W4)));
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EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromVectorRegister(W16)));
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EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromVectorRegister(W31)));
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reg = Mips64ManagedRegister::FromGpuRegister(S0);
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EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromGpuRegister(ZERO)));
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EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromGpuRegister(A0)));
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EXPECT_TRUE(reg.Overlaps(Mips64ManagedRegister::FromGpuRegister(S0)));
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EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromGpuRegister(RA)));
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EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromFpuRegister(F0)));
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EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromFpuRegister(F4)));
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EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromFpuRegister(F16)));
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EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromFpuRegister(F31)));
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EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromVectorRegister(W0)));
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EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromVectorRegister(W4)));
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EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromVectorRegister(W16)));
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EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromVectorRegister(W31)));
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reg = Mips64ManagedRegister::FromGpuRegister(RA);
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EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromGpuRegister(ZERO)));
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EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromGpuRegister(A0)));
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EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromGpuRegister(S0)));
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EXPECT_TRUE(reg.Overlaps(Mips64ManagedRegister::FromGpuRegister(RA)));
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EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromFpuRegister(F0)));
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EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromFpuRegister(F4)));
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EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromFpuRegister(F16)));
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EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromFpuRegister(F31)));
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EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromVectorRegister(W0)));
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EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromVectorRegister(W4)));
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EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromVectorRegister(W16)));
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EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromVectorRegister(W31)));
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}
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} // namespace mips64
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} // namespace art
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