/*
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* Copyright (C) 2014 The Android Open Source Project
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#include "register_allocator_linear_scan.h"
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#include <iostream>
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#include <sstream>
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#include "base/bit_vector-inl.h"
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#include "base/enums.h"
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#include "code_generator.h"
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#include "linear_order.h"
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#include "register_allocation_resolver.h"
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#include "ssa_liveness_analysis.h"
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namespace art {
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static constexpr size_t kMaxLifetimePosition = -1;
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static constexpr size_t kDefaultNumberOfSpillSlots = 4;
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// For simplicity, we implement register pairs as (reg, reg + 1).
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// Note that this is a requirement for double registers on ARM, since we
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// allocate SRegister.
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static int GetHighForLowRegister(int reg) { return reg + 1; }
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static bool IsLowRegister(int reg) { return (reg & 1) == 0; }
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static bool IsLowOfUnalignedPairInterval(LiveInterval* low) {
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return GetHighForLowRegister(low->GetRegister()) != low->GetHighInterval()->GetRegister();
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}
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RegisterAllocatorLinearScan::RegisterAllocatorLinearScan(ScopedArenaAllocator* allocator,
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CodeGenerator* codegen,
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const SsaLivenessAnalysis& liveness)
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: RegisterAllocator(allocator, codegen, liveness),
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unhandled_core_intervals_(allocator->Adapter(kArenaAllocRegisterAllocator)),
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unhandled_fp_intervals_(allocator->Adapter(kArenaAllocRegisterAllocator)),
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unhandled_(nullptr),
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handled_(allocator->Adapter(kArenaAllocRegisterAllocator)),
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active_(allocator->Adapter(kArenaAllocRegisterAllocator)),
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inactive_(allocator->Adapter(kArenaAllocRegisterAllocator)),
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physical_core_register_intervals_(allocator->Adapter(kArenaAllocRegisterAllocator)),
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physical_fp_register_intervals_(allocator->Adapter(kArenaAllocRegisterAllocator)),
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temp_intervals_(allocator->Adapter(kArenaAllocRegisterAllocator)),
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int_spill_slots_(allocator->Adapter(kArenaAllocRegisterAllocator)),
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long_spill_slots_(allocator->Adapter(kArenaAllocRegisterAllocator)),
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float_spill_slots_(allocator->Adapter(kArenaAllocRegisterAllocator)),
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double_spill_slots_(allocator->Adapter(kArenaAllocRegisterAllocator)),
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catch_phi_spill_slots_(0),
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safepoints_(allocator->Adapter(kArenaAllocRegisterAllocator)),
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processing_core_registers_(false),
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number_of_registers_(-1),
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registers_array_(nullptr),
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blocked_core_registers_(codegen->GetBlockedCoreRegisters()),
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blocked_fp_registers_(codegen->GetBlockedFloatingPointRegisters()),
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reserved_out_slots_(0) {
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temp_intervals_.reserve(4);
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int_spill_slots_.reserve(kDefaultNumberOfSpillSlots);
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long_spill_slots_.reserve(kDefaultNumberOfSpillSlots);
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float_spill_slots_.reserve(kDefaultNumberOfSpillSlots);
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double_spill_slots_.reserve(kDefaultNumberOfSpillSlots);
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codegen->SetupBlockedRegisters();
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physical_core_register_intervals_.resize(codegen->GetNumberOfCoreRegisters(), nullptr);
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physical_fp_register_intervals_.resize(codegen->GetNumberOfFloatingPointRegisters(), nullptr);
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// Always reserve for the current method and the graph's max out registers.
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// TODO: compute it instead.
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// ArtMethod* takes 2 vregs for 64 bits.
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size_t ptr_size = static_cast<size_t>(InstructionSetPointerSize(codegen->GetInstructionSet()));
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reserved_out_slots_ = ptr_size / kVRegSize + codegen->GetGraph()->GetMaximumNumberOfOutVRegs();
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}
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RegisterAllocatorLinearScan::~RegisterAllocatorLinearScan() {}
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static bool ShouldProcess(bool processing_core_registers, LiveInterval* interval) {
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if (interval == nullptr) return false;
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bool is_core_register = (interval->GetType() != DataType::Type::kFloat64)
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&& (interval->GetType() != DataType::Type::kFloat32);
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return processing_core_registers == is_core_register;
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}
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void RegisterAllocatorLinearScan::AllocateRegisters() {
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AllocateRegistersInternal();
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RegisterAllocationResolver(codegen_, liveness_)
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.Resolve(ArrayRef<HInstruction* const>(safepoints_),
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reserved_out_slots_,
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int_spill_slots_.size(),
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long_spill_slots_.size(),
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float_spill_slots_.size(),
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double_spill_slots_.size(),
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catch_phi_spill_slots_,
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ArrayRef<LiveInterval* const>(temp_intervals_));
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if (kIsDebugBuild) {
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processing_core_registers_ = true;
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ValidateInternal(true);
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processing_core_registers_ = false;
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ValidateInternal(true);
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// Check that the linear order is still correct with regards to lifetime positions.
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// Since only parallel moves have been inserted during the register allocation,
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// these checks are mostly for making sure these moves have been added correctly.
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size_t current_liveness = 0;
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for (HBasicBlock* block : codegen_->GetGraph()->GetLinearOrder()) {
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for (HInstructionIterator inst_it(block->GetPhis()); !inst_it.Done(); inst_it.Advance()) {
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HInstruction* instruction = inst_it.Current();
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DCHECK_LE(current_liveness, instruction->GetLifetimePosition());
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current_liveness = instruction->GetLifetimePosition();
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}
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for (HInstructionIterator inst_it(block->GetInstructions());
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!inst_it.Done();
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inst_it.Advance()) {
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HInstruction* instruction = inst_it.Current();
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DCHECK_LE(current_liveness, instruction->GetLifetimePosition()) << instruction->DebugName();
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current_liveness = instruction->GetLifetimePosition();
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}
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}
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}
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}
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void RegisterAllocatorLinearScan::BlockRegister(Location location, size_t start, size_t end) {
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int reg = location.reg();
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DCHECK(location.IsRegister() || location.IsFpuRegister());
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LiveInterval* interval = location.IsRegister()
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? physical_core_register_intervals_[reg]
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: physical_fp_register_intervals_[reg];
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DataType::Type type = location.IsRegister()
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? DataType::Type::kInt32
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: DataType::Type::kFloat32;
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if (interval == nullptr) {
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interval = LiveInterval::MakeFixedInterval(allocator_, reg, type);
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if (location.IsRegister()) {
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physical_core_register_intervals_[reg] = interval;
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} else {
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physical_fp_register_intervals_[reg] = interval;
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}
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}
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DCHECK(interval->GetRegister() == reg);
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interval->AddRange(start, end);
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}
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void RegisterAllocatorLinearScan::BlockRegisters(size_t start, size_t end, bool caller_save_only) {
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for (size_t i = 0; i < codegen_->GetNumberOfCoreRegisters(); ++i) {
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if (!caller_save_only || !codegen_->IsCoreCalleeSaveRegister(i)) {
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BlockRegister(Location::RegisterLocation(i), start, end);
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}
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}
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for (size_t i = 0; i < codegen_->GetNumberOfFloatingPointRegisters(); ++i) {
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if (!caller_save_only || !codegen_->IsFloatingPointCalleeSaveRegister(i)) {
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BlockRegister(Location::FpuRegisterLocation(i), start, end);
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}
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}
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}
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void RegisterAllocatorLinearScan::AllocateRegistersInternal() {
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// Iterate post-order, to ensure the list is sorted, and the last added interval
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// is the one with the lowest start position.
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for (HBasicBlock* block : codegen_->GetGraph()->GetLinearPostOrder()) {
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for (HBackwardInstructionIterator back_it(block->GetInstructions()); !back_it.Done();
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back_it.Advance()) {
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ProcessInstruction(back_it.Current());
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}
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for (HInstructionIterator inst_it(block->GetPhis()); !inst_it.Done(); inst_it.Advance()) {
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ProcessInstruction(inst_it.Current());
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}
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if (block->IsCatchBlock() ||
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(block->IsLoopHeader() && block->GetLoopInformation()->IsIrreducible())) {
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// By blocking all registers at the top of each catch block or irreducible loop, we force
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// intervals belonging to the live-in set of the catch/header block to be spilled.
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// TODO(ngeoffray): Phis in this block could be allocated in register.
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size_t position = block->GetLifetimeStart();
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BlockRegisters(position, position + 1);
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}
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}
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number_of_registers_ = codegen_->GetNumberOfCoreRegisters();
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registers_array_ = allocator_->AllocArray<size_t>(number_of_registers_,
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kArenaAllocRegisterAllocator);
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processing_core_registers_ = true;
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unhandled_ = &unhandled_core_intervals_;
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for (LiveInterval* fixed : physical_core_register_intervals_) {
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if (fixed != nullptr) {
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// Fixed interval is added to inactive_ instead of unhandled_.
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// It's also the only type of inactive interval whose start position
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// can be after the current interval during linear scan.
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// Fixed interval is never split and never moves to unhandled_.
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inactive_.push_back(fixed);
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}
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}
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LinearScan();
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inactive_.clear();
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active_.clear();
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handled_.clear();
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number_of_registers_ = codegen_->GetNumberOfFloatingPointRegisters();
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registers_array_ = allocator_->AllocArray<size_t>(number_of_registers_,
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kArenaAllocRegisterAllocator);
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processing_core_registers_ = false;
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unhandled_ = &unhandled_fp_intervals_;
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for (LiveInterval* fixed : physical_fp_register_intervals_) {
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if (fixed != nullptr) {
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// Fixed interval is added to inactive_ instead of unhandled_.
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// It's also the only type of inactive interval whose start position
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// can be after the current interval during linear scan.
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// Fixed interval is never split and never moves to unhandled_.
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inactive_.push_back(fixed);
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}
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}
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LinearScan();
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}
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void RegisterAllocatorLinearScan::ProcessInstruction(HInstruction* instruction) {
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LocationSummary* locations = instruction->GetLocations();
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size_t position = instruction->GetLifetimePosition();
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if (locations == nullptr) return;
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// Create synthesized intervals for temporaries.
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for (size_t i = 0; i < locations->GetTempCount(); ++i) {
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Location temp = locations->GetTemp(i);
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if (temp.IsRegister() || temp.IsFpuRegister()) {
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BlockRegister(temp, position, position + 1);
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// Ensure that an explicit temporary register is marked as being allocated.
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codegen_->AddAllocatedRegister(temp);
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} else {
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DCHECK(temp.IsUnallocated());
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switch (temp.GetPolicy()) {
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case Location::kRequiresRegister: {
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LiveInterval* interval =
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LiveInterval::MakeTempInterval(allocator_, DataType::Type::kInt32);
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temp_intervals_.push_back(interval);
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interval->AddTempUse(instruction, i);
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unhandled_core_intervals_.push_back(interval);
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break;
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}
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case Location::kRequiresFpuRegister: {
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LiveInterval* interval =
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LiveInterval::MakeTempInterval(allocator_, DataType::Type::kFloat64);
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temp_intervals_.push_back(interval);
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interval->AddTempUse(instruction, i);
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if (codegen_->NeedsTwoRegisters(DataType::Type::kFloat64)) {
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interval->AddHighInterval(/* is_temp= */ true);
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LiveInterval* high = interval->GetHighInterval();
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temp_intervals_.push_back(high);
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unhandled_fp_intervals_.push_back(high);
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}
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unhandled_fp_intervals_.push_back(interval);
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break;
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}
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default:
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LOG(FATAL) << "Unexpected policy for temporary location "
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<< temp.GetPolicy();
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}
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}
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}
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bool core_register = (instruction->GetType() != DataType::Type::kFloat64)
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&& (instruction->GetType() != DataType::Type::kFloat32);
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if (locations->NeedsSafepoint()) {
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if (codegen_->IsLeafMethod()) {
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// TODO: We do this here because we do not want the suspend check to artificially
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// create live registers. We should find another place, but this is currently the
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// simplest.
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DCHECK(instruction->IsSuspendCheckEntry());
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instruction->GetBlock()->RemoveInstruction(instruction);
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return;
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}
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safepoints_.push_back(instruction);
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}
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if (locations->WillCall()) {
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BlockRegisters(position, position + 1, /* caller_save_only= */ true);
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}
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for (size_t i = 0; i < locations->GetInputCount(); ++i) {
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Location input = locations->InAt(i);
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if (input.IsRegister() || input.IsFpuRegister()) {
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BlockRegister(input, position, position + 1);
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} else if (input.IsPair()) {
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BlockRegister(input.ToLow(), position, position + 1);
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BlockRegister(input.ToHigh(), position, position + 1);
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}
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}
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LiveInterval* current = instruction->GetLiveInterval();
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if (current == nullptr) return;
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ScopedArenaVector<LiveInterval*>& unhandled = core_register
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? unhandled_core_intervals_
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: unhandled_fp_intervals_;
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DCHECK(unhandled.empty() || current->StartsBeforeOrAt(unhandled.back()));
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if (codegen_->NeedsTwoRegisters(current->GetType())) {
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current->AddHighInterval();
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}
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for (size_t safepoint_index = safepoints_.size(); safepoint_index > 0; --safepoint_index) {
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HInstruction* safepoint = safepoints_[safepoint_index - 1u];
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size_t safepoint_position = SafepointPosition::ComputePosition(safepoint);
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// Test that safepoints are ordered in the optimal way.
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DCHECK(safepoint_index == safepoints_.size() ||
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safepoints_[safepoint_index]->GetLifetimePosition() < safepoint_position);
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if (safepoint_position == current->GetStart()) {
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// The safepoint is for this instruction, so the location of the instruction
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// does not need to be saved.
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DCHECK_EQ(safepoint_index, safepoints_.size());
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DCHECK_EQ(safepoint, instruction);
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continue;
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} else if (current->IsDeadAt(safepoint_position)) {
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break;
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} else if (!current->Covers(safepoint_position)) {
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// Hole in the interval.
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continue;
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}
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current->AddSafepoint(safepoint);
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}
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current->ResetSearchCache();
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// Some instructions define their output in fixed register/stack slot. We need
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// to ensure we know these locations before doing register allocation. For a
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// given register, we create an interval that covers these locations. The register
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// will be unavailable at these locations when trying to allocate one for an
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// interval.
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//
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// The backwards walking ensures the ranges are ordered on increasing start positions.
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Location output = locations->Out();
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if (output.IsUnallocated() && output.GetPolicy() == Location::kSameAsFirstInput) {
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Location first = locations->InAt(0);
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if (first.IsRegister() || first.IsFpuRegister()) {
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current->SetFrom(position + 1);
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current->SetRegister(first.reg());
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} else if (first.IsPair()) {
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current->SetFrom(position + 1);
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current->SetRegister(first.low());
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LiveInterval* high = current->GetHighInterval();
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high->SetRegister(first.high());
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high->SetFrom(position + 1);
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}
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} else if (output.IsRegister() || output.IsFpuRegister()) {
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// Shift the interval's start by one to account for the blocked register.
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current->SetFrom(position + 1);
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current->SetRegister(output.reg());
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BlockRegister(output, position, position + 1);
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} else if (output.IsPair()) {
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current->SetFrom(position + 1);
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current->SetRegister(output.low());
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LiveInterval* high = current->GetHighInterval();
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high->SetRegister(output.high());
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high->SetFrom(position + 1);
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BlockRegister(output.ToLow(), position, position + 1);
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BlockRegister(output.ToHigh(), position, position + 1);
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} else if (output.IsStackSlot() || output.IsDoubleStackSlot()) {
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current->SetSpillSlot(output.GetStackIndex());
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} else {
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DCHECK(output.IsUnallocated() || output.IsConstant());
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}
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if (instruction->IsPhi() && instruction->AsPhi()->IsCatchPhi()) {
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AllocateSpillSlotForCatchPhi(instruction->AsPhi());
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}
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// If needed, add interval to the list of unhandled intervals.
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if (current->HasSpillSlot() || instruction->IsConstant()) {
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// Split just before first register use.
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size_t first_register_use = current->FirstRegisterUse();
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if (first_register_use != kNoLifetime) {
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LiveInterval* split = SplitBetween(current, current->GetStart(), first_register_use - 1);
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// Don't add directly to `unhandled`, it needs to be sorted and the start
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// of this new interval might be after intervals already in the list.
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AddSorted(&unhandled, split);
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} else {
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// Nothing to do, we won't allocate a register for this value.
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}
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} else {
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// Don't add directly to `unhandled`, temp or safepoint intervals
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// for this instruction may have been added, and those can be
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// processed first.
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AddSorted(&unhandled, current);
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}
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}
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class AllRangesIterator : public ValueObject {
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public:
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explicit AllRangesIterator(LiveInterval* interval)
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: current_interval_(interval),
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current_range_(interval->GetFirstRange()) {}
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bool Done() const { return current_interval_ == nullptr; }
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LiveRange* CurrentRange() const { return current_range_; }
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LiveInterval* CurrentInterval() const { return current_interval_; }
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void Advance() {
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current_range_ = current_range_->GetNext();
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if (current_range_ == nullptr) {
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current_interval_ = current_interval_->GetNextSibling();
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if (current_interval_ != nullptr) {
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current_range_ = current_interval_->GetFirstRange();
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}
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}
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}
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private:
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LiveInterval* current_interval_;
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LiveRange* current_range_;
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DISALLOW_COPY_AND_ASSIGN(AllRangesIterator);
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};
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bool RegisterAllocatorLinearScan::ValidateInternal(bool log_fatal_on_failure) const {
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// To simplify unit testing, we eagerly create the array of intervals, and
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// call the helper method.
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ScopedArenaAllocator allocator(allocator_->GetArenaStack());
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ScopedArenaVector<LiveInterval*> intervals(
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allocator.Adapter(kArenaAllocRegisterAllocatorValidate));
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for (size_t i = 0; i < liveness_.GetNumberOfSsaValues(); ++i) {
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HInstruction* instruction = liveness_.GetInstructionFromSsaIndex(i);
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if (ShouldProcess(processing_core_registers_, instruction->GetLiveInterval())) {
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intervals.push_back(instruction->GetLiveInterval());
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}
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}
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const ScopedArenaVector<LiveInterval*>* physical_register_intervals = processing_core_registers_
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? &physical_core_register_intervals_
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: &physical_fp_register_intervals_;
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for (LiveInterval* fixed : *physical_register_intervals) {
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if (fixed != nullptr) {
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intervals.push_back(fixed);
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}
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}
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for (LiveInterval* temp : temp_intervals_) {
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if (ShouldProcess(processing_core_registers_, temp)) {
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intervals.push_back(temp);
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}
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}
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return ValidateIntervals(ArrayRef<LiveInterval* const>(intervals),
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GetNumberOfSpillSlots(),
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reserved_out_slots_,
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*codegen_,
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processing_core_registers_,
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log_fatal_on_failure);
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}
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void RegisterAllocatorLinearScan::DumpInterval(std::ostream& stream, LiveInterval* interval) const {
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interval->Dump(stream);
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stream << ": ";
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if (interval->HasRegister()) {
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if (interval->IsFloatingPoint()) {
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codegen_->DumpFloatingPointRegister(stream, interval->GetRegister());
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} else {
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codegen_->DumpCoreRegister(stream, interval->GetRegister());
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}
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} else {
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stream << "spilled";
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}
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stream << std::endl;
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}
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void RegisterAllocatorLinearScan::DumpAllIntervals(std::ostream& stream) const {
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stream << "inactive: " << std::endl;
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for (LiveInterval* inactive_interval : inactive_) {
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DumpInterval(stream, inactive_interval);
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}
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stream << "active: " << std::endl;
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for (LiveInterval* active_interval : active_) {
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DumpInterval(stream, active_interval);
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}
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stream << "unhandled: " << std::endl;
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auto unhandled = (unhandled_ != nullptr) ?
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unhandled_ : &unhandled_core_intervals_;
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for (LiveInterval* unhandled_interval : *unhandled) {
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DumpInterval(stream, unhandled_interval);
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}
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stream << "handled: " << std::endl;
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for (LiveInterval* handled_interval : handled_) {
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DumpInterval(stream, handled_interval);
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}
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}
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// By the book implementation of a linear scan register allocator.
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void RegisterAllocatorLinearScan::LinearScan() {
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while (!unhandled_->empty()) {
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// (1) Remove interval with the lowest start position from unhandled.
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LiveInterval* current = unhandled_->back();
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unhandled_->pop_back();
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// Make sure the interval is an expected state.
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DCHECK(!current->IsFixed() && !current->HasSpillSlot());
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// Make sure we are going in the right order.
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DCHECK(unhandled_->empty() || unhandled_->back()->GetStart() >= current->GetStart());
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// Make sure a low interval is always with a high.
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DCHECK(!current->IsLowInterval() || unhandled_->back()->IsHighInterval());
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// Make sure a high interval is always with a low.
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DCHECK(current->IsLowInterval() ||
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unhandled_->empty() ||
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!unhandled_->back()->IsHighInterval());
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size_t position = current->GetStart();
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// Remember the inactive_ size here since the ones moved to inactive_ from
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// active_ below shouldn't need to be re-checked.
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size_t inactive_intervals_to_handle = inactive_.size();
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// (2) Remove currently active intervals that are dead at this position.
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// Move active intervals that have a lifetime hole at this position
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// to inactive.
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auto active_kept_end = std::remove_if(
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active_.begin(),
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active_.end(),
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[this, position](LiveInterval* interval) {
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if (interval->IsDeadAt(position)) {
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handled_.push_back(interval);
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return true;
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} else if (!interval->Covers(position)) {
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inactive_.push_back(interval);
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return true;
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} else {
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return false; // Keep this interval.
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}
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});
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active_.erase(active_kept_end, active_.end());
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// (3) Remove currently inactive intervals that are dead at this position.
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// Move inactive intervals that cover this position to active.
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auto inactive_to_handle_end = inactive_.begin() + inactive_intervals_to_handle;
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auto inactive_kept_end = std::remove_if(
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inactive_.begin(),
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inactive_to_handle_end,
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[this, position](LiveInterval* interval) {
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DCHECK(interval->GetStart() < position || interval->IsFixed());
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if (interval->IsDeadAt(position)) {
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handled_.push_back(interval);
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return true;
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} else if (interval->Covers(position)) {
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active_.push_back(interval);
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return true;
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} else {
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return false; // Keep this interval.
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}
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});
|
inactive_.erase(inactive_kept_end, inactive_to_handle_end);
|
|
if (current->IsHighInterval() && !current->GetLowInterval()->HasRegister()) {
|
DCHECK(!current->HasRegister());
|
// Allocating the low part was unsucessful. The splitted interval for the high part
|
// will be handled next (it is in the `unhandled_` list).
|
continue;
|
}
|
|
// (4) Try to find an available register.
|
bool success = TryAllocateFreeReg(current);
|
|
// (5) If no register could be found, we need to spill.
|
if (!success) {
|
success = AllocateBlockedReg(current);
|
}
|
|
// (6) If the interval had a register allocated, add it to the list of active
|
// intervals.
|
if (success) {
|
codegen_->AddAllocatedRegister(processing_core_registers_
|
? Location::RegisterLocation(current->GetRegister())
|
: Location::FpuRegisterLocation(current->GetRegister()));
|
active_.push_back(current);
|
if (current->HasHighInterval() && !current->GetHighInterval()->HasRegister()) {
|
current->GetHighInterval()->SetRegister(GetHighForLowRegister(current->GetRegister()));
|
}
|
}
|
}
|
}
|
|
static void FreeIfNotCoverAt(LiveInterval* interval, size_t position, size_t* free_until) {
|
DCHECK(!interval->IsHighInterval());
|
// Note that the same instruction may occur multiple times in the input list,
|
// so `free_until` may have changed already.
|
// Since `position` is not the current scan position, we need to use CoversSlow.
|
if (interval->IsDeadAt(position)) {
|
// Set the register to be free. Note that inactive intervals might later
|
// update this.
|
free_until[interval->GetRegister()] = kMaxLifetimePosition;
|
if (interval->HasHighInterval()) {
|
DCHECK(interval->GetHighInterval()->IsDeadAt(position));
|
free_until[interval->GetHighInterval()->GetRegister()] = kMaxLifetimePosition;
|
}
|
} else if (!interval->CoversSlow(position)) {
|
// The interval becomes inactive at `defined_by`. We make its register
|
// available only until the next use strictly after `defined_by`.
|
free_until[interval->GetRegister()] = interval->FirstUseAfter(position);
|
if (interval->HasHighInterval()) {
|
DCHECK(!interval->GetHighInterval()->CoversSlow(position));
|
free_until[interval->GetHighInterval()->GetRegister()] = free_until[interval->GetRegister()];
|
}
|
}
|
}
|
|
// Find a free register. If multiple are found, pick the register that
|
// is free the longest.
|
bool RegisterAllocatorLinearScan::TryAllocateFreeReg(LiveInterval* current) {
|
size_t* free_until = registers_array_;
|
|
// First set all registers to be free.
|
for (size_t i = 0; i < number_of_registers_; ++i) {
|
free_until[i] = kMaxLifetimePosition;
|
}
|
|
// For each active interval, set its register to not free.
|
for (LiveInterval* interval : active_) {
|
DCHECK(interval->HasRegister());
|
free_until[interval->GetRegister()] = 0;
|
}
|
|
// An interval that starts an instruction (that is, it is not split), may
|
// re-use the registers used by the inputs of that instruciton, based on the
|
// location summary.
|
HInstruction* defined_by = current->GetDefinedBy();
|
if (defined_by != nullptr && !current->IsSplit()) {
|
LocationSummary* locations = defined_by->GetLocations();
|
if (!locations->OutputCanOverlapWithInputs() && locations->Out().IsUnallocated()) {
|
HInputsRef inputs = defined_by->GetInputs();
|
for (size_t i = 0; i < inputs.size(); ++i) {
|
if (locations->InAt(i).IsValid()) {
|
// Take the last interval of the input. It is the location of that interval
|
// that will be used at `defined_by`.
|
LiveInterval* interval = inputs[i]->GetLiveInterval()->GetLastSibling();
|
// Note that interval may have not been processed yet.
|
// TODO: Handle non-split intervals last in the work list.
|
if (interval->HasRegister() && interval->SameRegisterKind(*current)) {
|
// The input must be live until the end of `defined_by`, to comply to
|
// the linear scan algorithm. So we use `defined_by`'s end lifetime
|
// position to check whether the input is dead or is inactive after
|
// `defined_by`.
|
DCHECK(interval->CoversSlow(defined_by->GetLifetimePosition()));
|
size_t position = defined_by->GetLifetimePosition() + 1;
|
FreeIfNotCoverAt(interval, position, free_until);
|
}
|
}
|
}
|
}
|
}
|
|
// For each inactive interval, set its register to be free until
|
// the next intersection with `current`.
|
for (LiveInterval* inactive : inactive_) {
|
// Temp/Slow-path-safepoint interval has no holes.
|
DCHECK(!inactive->IsTemp());
|
if (!current->IsSplit() && !inactive->IsFixed()) {
|
// Neither current nor inactive are fixed.
|
// Thanks to SSA, a non-split interval starting in a hole of an
|
// inactive interval should never intersect with that inactive interval.
|
// Only if it's not fixed though, because fixed intervals don't come from SSA.
|
DCHECK_EQ(inactive->FirstIntersectionWith(current), kNoLifetime);
|
continue;
|
}
|
|
DCHECK(inactive->HasRegister());
|
if (free_until[inactive->GetRegister()] == 0) {
|
// Already used by some active interval. No need to intersect.
|
continue;
|
}
|
size_t next_intersection = inactive->FirstIntersectionWith(current);
|
if (next_intersection != kNoLifetime) {
|
free_until[inactive->GetRegister()] =
|
std::min(free_until[inactive->GetRegister()], next_intersection);
|
}
|
}
|
|
int reg = kNoRegister;
|
if (current->HasRegister()) {
|
// Some instructions have a fixed register output.
|
reg = current->GetRegister();
|
if (free_until[reg] == 0) {
|
DCHECK(current->IsHighInterval());
|
// AllocateBlockedReg will spill the holder of the register.
|
return false;
|
}
|
} else {
|
DCHECK(!current->IsHighInterval());
|
int hint = current->FindFirstRegisterHint(free_until, liveness_);
|
if ((hint != kNoRegister)
|
// For simplicity, if the hint we are getting for a pair cannot be used,
|
// we are just going to allocate a new pair.
|
&& !(current->IsLowInterval() && IsBlocked(GetHighForLowRegister(hint)))) {
|
DCHECK(!IsBlocked(hint));
|
reg = hint;
|
} else if (current->IsLowInterval()) {
|
reg = FindAvailableRegisterPair(free_until, current->GetStart());
|
} else {
|
reg = FindAvailableRegister(free_until, current);
|
}
|
}
|
|
DCHECK_NE(reg, kNoRegister);
|
// If we could not find a register, we need to spill.
|
if (free_until[reg] == 0) {
|
return false;
|
}
|
|
if (current->IsLowInterval()) {
|
// If the high register of this interval is not available, we need to spill.
|
int high_reg = current->GetHighInterval()->GetRegister();
|
if (high_reg == kNoRegister) {
|
high_reg = GetHighForLowRegister(reg);
|
}
|
if (free_until[high_reg] == 0) {
|
return false;
|
}
|
}
|
|
current->SetRegister(reg);
|
if (!current->IsDeadAt(free_until[reg])) {
|
// If the register is only available for a subset of live ranges
|
// covered by `current`, split `current` before the position where
|
// the register is not available anymore.
|
LiveInterval* split = SplitBetween(current, current->GetStart(), free_until[reg]);
|
DCHECK(split != nullptr);
|
AddSorted(unhandled_, split);
|
}
|
return true;
|
}
|
|
bool RegisterAllocatorLinearScan::IsBlocked(int reg) const {
|
return processing_core_registers_
|
? blocked_core_registers_[reg]
|
: blocked_fp_registers_[reg];
|
}
|
|
int RegisterAllocatorLinearScan::FindAvailableRegisterPair(size_t* next_use, size_t starting_at) const {
|
int reg = kNoRegister;
|
// Pick the register pair that is used the last.
|
for (size_t i = 0; i < number_of_registers_; ++i) {
|
if (IsBlocked(i)) continue;
|
if (!IsLowRegister(i)) continue;
|
int high_register = GetHighForLowRegister(i);
|
if (IsBlocked(high_register)) continue;
|
int existing_high_register = GetHighForLowRegister(reg);
|
if ((reg == kNoRegister) || (next_use[i] >= next_use[reg]
|
&& next_use[high_register] >= next_use[existing_high_register])) {
|
reg = i;
|
if (next_use[i] == kMaxLifetimePosition
|
&& next_use[high_register] == kMaxLifetimePosition) {
|
break;
|
}
|
} else if (next_use[reg] <= starting_at || next_use[existing_high_register] <= starting_at) {
|
// If one of the current register is known to be unavailable, just unconditionally
|
// try a new one.
|
reg = i;
|
}
|
}
|
return reg;
|
}
|
|
bool RegisterAllocatorLinearScan::IsCallerSaveRegister(int reg) const {
|
return processing_core_registers_
|
? !codegen_->IsCoreCalleeSaveRegister(reg)
|
: !codegen_->IsFloatingPointCalleeSaveRegister(reg);
|
}
|
|
int RegisterAllocatorLinearScan::FindAvailableRegister(size_t* next_use, LiveInterval* current) const {
|
// We special case intervals that do not span a safepoint to try to find a caller-save
|
// register if one is available. We iterate from 0 to the number of registers,
|
// so if there are caller-save registers available at the end, we continue the iteration.
|
bool prefers_caller_save = !current->HasWillCallSafepoint();
|
int reg = kNoRegister;
|
for (size_t i = 0; i < number_of_registers_; ++i) {
|
if (IsBlocked(i)) {
|
// Register cannot be used. Continue.
|
continue;
|
}
|
|
// Best case: we found a register fully available.
|
if (next_use[i] == kMaxLifetimePosition) {
|
if (prefers_caller_save && !IsCallerSaveRegister(i)) {
|
// We can get shorter encodings on some platforms by using
|
// small register numbers. So only update the candidate if the previous
|
// one was not available for the whole method.
|
if (reg == kNoRegister || next_use[reg] != kMaxLifetimePosition) {
|
reg = i;
|
}
|
// Continue the iteration in the hope of finding a caller save register.
|
continue;
|
} else {
|
reg = i;
|
// We know the register is good enough. Return it.
|
break;
|
}
|
}
|
|
// If we had no register before, take this one as a reference.
|
if (reg == kNoRegister) {
|
reg = i;
|
continue;
|
}
|
|
// Pick the register that is used the last.
|
if (next_use[i] > next_use[reg]) {
|
reg = i;
|
continue;
|
}
|
}
|
return reg;
|
}
|
|
// Remove interval and its other half if any. Return iterator to the following element.
|
static ArenaVector<LiveInterval*>::iterator RemoveIntervalAndPotentialOtherHalf(
|
ScopedArenaVector<LiveInterval*>* intervals, ScopedArenaVector<LiveInterval*>::iterator pos) {
|
DCHECK(intervals->begin() <= pos && pos < intervals->end());
|
LiveInterval* interval = *pos;
|
if (interval->IsLowInterval()) {
|
DCHECK(pos + 1 < intervals->end());
|
DCHECK_EQ(*(pos + 1), interval->GetHighInterval());
|
return intervals->erase(pos, pos + 2);
|
} else if (interval->IsHighInterval()) {
|
DCHECK(intervals->begin() < pos);
|
DCHECK_EQ(*(pos - 1), interval->GetLowInterval());
|
return intervals->erase(pos - 1, pos + 1);
|
} else {
|
return intervals->erase(pos);
|
}
|
}
|
|
bool RegisterAllocatorLinearScan::TrySplitNonPairOrUnalignedPairIntervalAt(size_t position,
|
size_t first_register_use,
|
size_t* next_use) {
|
for (auto it = active_.begin(), end = active_.end(); it != end; ++it) {
|
LiveInterval* active = *it;
|
DCHECK(active->HasRegister());
|
if (active->IsFixed()) continue;
|
if (active->IsHighInterval()) continue;
|
if (first_register_use > next_use[active->GetRegister()]) continue;
|
|
// Split the first interval found that is either:
|
// 1) A non-pair interval.
|
// 2) A pair interval whose high is not low + 1.
|
// 3) A pair interval whose low is not even.
|
if (!active->IsLowInterval() ||
|
IsLowOfUnalignedPairInterval(active) ||
|
!IsLowRegister(active->GetRegister())) {
|
LiveInterval* split = Split(active, position);
|
if (split != active) {
|
handled_.push_back(active);
|
}
|
RemoveIntervalAndPotentialOtherHalf(&active_, it);
|
AddSorted(unhandled_, split);
|
return true;
|
}
|
}
|
return false;
|
}
|
|
// Find the register that is used the last, and spill the interval
|
// that holds it. If the first use of `current` is after that register
|
// we spill `current` instead.
|
bool RegisterAllocatorLinearScan::AllocateBlockedReg(LiveInterval* current) {
|
size_t first_register_use = current->FirstRegisterUse();
|
if (current->HasRegister()) {
|
DCHECK(current->IsHighInterval());
|
// The low interval has allocated the register for the high interval. In
|
// case the low interval had to split both intervals, we may end up in a
|
// situation where the high interval does not have a register use anymore.
|
// We must still proceed in order to split currently active and inactive
|
// uses of the high interval's register, and put the high interval in the
|
// active set.
|
DCHECK(first_register_use != kNoLifetime || (current->GetNextSibling() != nullptr));
|
} else if (first_register_use == kNoLifetime) {
|
AllocateSpillSlotFor(current);
|
return false;
|
}
|
|
// First set all registers as not being used.
|
size_t* next_use = registers_array_;
|
for (size_t i = 0; i < number_of_registers_; ++i) {
|
next_use[i] = kMaxLifetimePosition;
|
}
|
|
// For each active interval, find the next use of its register after the
|
// start of current.
|
for (LiveInterval* active : active_) {
|
DCHECK(active->HasRegister());
|
if (active->IsFixed()) {
|
next_use[active->GetRegister()] = current->GetStart();
|
} else {
|
size_t use = active->FirstRegisterUseAfter(current->GetStart());
|
if (use != kNoLifetime) {
|
next_use[active->GetRegister()] = use;
|
}
|
}
|
}
|
|
// For each inactive interval, find the next use of its register after the
|
// start of current.
|
for (LiveInterval* inactive : inactive_) {
|
// Temp/Slow-path-safepoint interval has no holes.
|
DCHECK(!inactive->IsTemp());
|
if (!current->IsSplit() && !inactive->IsFixed()) {
|
// Neither current nor inactive are fixed.
|
// Thanks to SSA, a non-split interval starting in a hole of an
|
// inactive interval should never intersect with that inactive interval.
|
// Only if it's not fixed though, because fixed intervals don't come from SSA.
|
DCHECK_EQ(inactive->FirstIntersectionWith(current), kNoLifetime);
|
continue;
|
}
|
DCHECK(inactive->HasRegister());
|
size_t next_intersection = inactive->FirstIntersectionWith(current);
|
if (next_intersection != kNoLifetime) {
|
if (inactive->IsFixed()) {
|
next_use[inactive->GetRegister()] =
|
std::min(next_intersection, next_use[inactive->GetRegister()]);
|
} else {
|
size_t use = inactive->FirstUseAfter(current->GetStart());
|
if (use != kNoLifetime) {
|
next_use[inactive->GetRegister()] = std::min(use, next_use[inactive->GetRegister()]);
|
}
|
}
|
}
|
}
|
|
int reg = kNoRegister;
|
bool should_spill = false;
|
if (current->HasRegister()) {
|
DCHECK(current->IsHighInterval());
|
reg = current->GetRegister();
|
// When allocating the low part, we made sure the high register was available.
|
DCHECK_LT(first_register_use, next_use[reg]);
|
} else if (current->IsLowInterval()) {
|
reg = FindAvailableRegisterPair(next_use, first_register_use);
|
// We should spill if both registers are not available.
|
should_spill = (first_register_use >= next_use[reg])
|
|| (first_register_use >= next_use[GetHighForLowRegister(reg)]);
|
} else {
|
DCHECK(!current->IsHighInterval());
|
reg = FindAvailableRegister(next_use, current);
|
should_spill = (first_register_use >= next_use[reg]);
|
}
|
|
DCHECK_NE(reg, kNoRegister);
|
if (should_spill) {
|
DCHECK(!current->IsHighInterval());
|
bool is_allocation_at_use_site = (current->GetStart() >= (first_register_use - 1));
|
if (is_allocation_at_use_site) {
|
if (!current->IsLowInterval()) {
|
DumpInterval(std::cerr, current);
|
DumpAllIntervals(std::cerr);
|
// This situation has the potential to infinite loop, so we make it a non-debug CHECK.
|
HInstruction* at = liveness_.GetInstructionFromPosition(first_register_use / 2);
|
CHECK(false) << "There is not enough registers available for "
|
<< current->GetParent()->GetDefinedBy()->DebugName() << " "
|
<< current->GetParent()->GetDefinedBy()->GetId()
|
<< " at " << first_register_use - 1 << " "
|
<< (at == nullptr ? "" : at->DebugName());
|
}
|
|
// If we're allocating a register for `current` because the instruction at
|
// that position requires it, but we think we should spill, then there are
|
// non-pair intervals or unaligned pair intervals blocking the allocation.
|
// We split the first interval found, and put ourselves first in the
|
// `unhandled_` list.
|
bool success = TrySplitNonPairOrUnalignedPairIntervalAt(current->GetStart(),
|
first_register_use,
|
next_use);
|
DCHECK(success);
|
LiveInterval* existing = unhandled_->back();
|
DCHECK(existing->IsHighInterval());
|
DCHECK_EQ(existing->GetLowInterval(), current);
|
unhandled_->push_back(current);
|
} else {
|
// If the first use of that instruction is after the last use of the found
|
// register, we split this interval just before its first register use.
|
AllocateSpillSlotFor(current);
|
LiveInterval* split = SplitBetween(current, current->GetStart(), first_register_use - 1);
|
DCHECK(current != split);
|
AddSorted(unhandled_, split);
|
}
|
return false;
|
} else {
|
// Use this register and spill the active and inactives interval that
|
// have that register.
|
current->SetRegister(reg);
|
|
for (auto it = active_.begin(), end = active_.end(); it != end; ++it) {
|
LiveInterval* active = *it;
|
if (active->GetRegister() == reg) {
|
DCHECK(!active->IsFixed());
|
LiveInterval* split = Split(active, current->GetStart());
|
if (split != active) {
|
handled_.push_back(active);
|
}
|
RemoveIntervalAndPotentialOtherHalf(&active_, it);
|
AddSorted(unhandled_, split);
|
break;
|
}
|
}
|
|
// NOTE: Retrieve end() on each iteration because we're removing elements in the loop body.
|
for (auto it = inactive_.begin(); it != inactive_.end(); ) {
|
LiveInterval* inactive = *it;
|
bool erased = false;
|
if (inactive->GetRegister() == reg) {
|
if (!current->IsSplit() && !inactive->IsFixed()) {
|
// Neither current nor inactive are fixed.
|
// Thanks to SSA, a non-split interval starting in a hole of an
|
// inactive interval should never intersect with that inactive interval.
|
// Only if it's not fixed though, because fixed intervals don't come from SSA.
|
DCHECK_EQ(inactive->FirstIntersectionWith(current), kNoLifetime);
|
} else {
|
size_t next_intersection = inactive->FirstIntersectionWith(current);
|
if (next_intersection != kNoLifetime) {
|
if (inactive->IsFixed()) {
|
LiveInterval* split = Split(current, next_intersection);
|
DCHECK_NE(split, current);
|
AddSorted(unhandled_, split);
|
} else {
|
// Split at the start of `current`, which will lead to splitting
|
// at the end of the lifetime hole of `inactive`.
|
LiveInterval* split = Split(inactive, current->GetStart());
|
// If it's inactive, it must start before the current interval.
|
DCHECK_NE(split, inactive);
|
it = RemoveIntervalAndPotentialOtherHalf(&inactive_, it);
|
erased = true;
|
handled_.push_back(inactive);
|
AddSorted(unhandled_, split);
|
}
|
}
|
}
|
}
|
// If we have erased the element, `it` already points to the next element.
|
// Otherwise we need to move to the next element.
|
if (!erased) {
|
++it;
|
}
|
}
|
|
return true;
|
}
|
}
|
|
void RegisterAllocatorLinearScan::AddSorted(ScopedArenaVector<LiveInterval*>* array,
|
LiveInterval* interval) {
|
DCHECK(!interval->IsFixed() && !interval->HasSpillSlot());
|
size_t insert_at = 0;
|
for (size_t i = array->size(); i > 0; --i) {
|
LiveInterval* current = (*array)[i - 1u];
|
// High intervals must be processed right after their low equivalent.
|
if (current->StartsAfter(interval) && !current->IsHighInterval()) {
|
insert_at = i;
|
break;
|
}
|
}
|
|
// Insert the high interval before the low, to ensure the low is processed before.
|
auto insert_pos = array->begin() + insert_at;
|
if (interval->HasHighInterval()) {
|
array->insert(insert_pos, { interval->GetHighInterval(), interval });
|
} else if (interval->HasLowInterval()) {
|
array->insert(insert_pos, { interval, interval->GetLowInterval() });
|
} else {
|
array->insert(insert_pos, interval);
|
}
|
}
|
|
void RegisterAllocatorLinearScan::AllocateSpillSlotFor(LiveInterval* interval) {
|
if (interval->IsHighInterval()) {
|
// The low interval already took care of allocating the spill slot.
|
DCHECK(!interval->GetLowInterval()->HasRegister());
|
DCHECK(interval->GetLowInterval()->GetParent()->HasSpillSlot());
|
return;
|
}
|
|
LiveInterval* parent = interval->GetParent();
|
|
// An instruction gets a spill slot for its entire lifetime. If the parent
|
// of this interval already has a spill slot, there is nothing to do.
|
if (parent->HasSpillSlot()) {
|
return;
|
}
|
|
HInstruction* defined_by = parent->GetDefinedBy();
|
DCHECK(!defined_by->IsPhi() || !defined_by->AsPhi()->IsCatchPhi());
|
|
if (defined_by->IsParameterValue()) {
|
// Parameters have their own stack slot.
|
parent->SetSpillSlot(codegen_->GetStackSlotOfParameter(defined_by->AsParameterValue()));
|
return;
|
}
|
|
if (defined_by->IsCurrentMethod()) {
|
parent->SetSpillSlot(0);
|
return;
|
}
|
|
if (defined_by->IsConstant()) {
|
// Constants don't need a spill slot.
|
return;
|
}
|
|
ScopedArenaVector<size_t>* spill_slots = nullptr;
|
switch (interval->GetType()) {
|
case DataType::Type::kFloat64:
|
spill_slots = &double_spill_slots_;
|
break;
|
case DataType::Type::kInt64:
|
spill_slots = &long_spill_slots_;
|
break;
|
case DataType::Type::kFloat32:
|
spill_slots = &float_spill_slots_;
|
break;
|
case DataType::Type::kReference:
|
case DataType::Type::kInt32:
|
case DataType::Type::kUint16:
|
case DataType::Type::kUint8:
|
case DataType::Type::kInt8:
|
case DataType::Type::kBool:
|
case DataType::Type::kInt16:
|
spill_slots = &int_spill_slots_;
|
break;
|
case DataType::Type::kUint32:
|
case DataType::Type::kUint64:
|
case DataType::Type::kVoid:
|
LOG(FATAL) << "Unexpected type for interval " << interval->GetType();
|
}
|
|
// Find first available spill slots.
|
size_t number_of_spill_slots_needed = parent->NumberOfSpillSlotsNeeded();
|
size_t slot = 0;
|
for (size_t e = spill_slots->size(); slot < e; ++slot) {
|
bool found = true;
|
for (size_t s = slot, u = std::min(slot + number_of_spill_slots_needed, e); s < u; s++) {
|
if ((*spill_slots)[s] > parent->GetStart()) {
|
found = false; // failure
|
break;
|
}
|
}
|
if (found) {
|
break; // success
|
}
|
}
|
|
// Need new spill slots?
|
size_t upper = slot + number_of_spill_slots_needed;
|
if (upper > spill_slots->size()) {
|
spill_slots->resize(upper);
|
}
|
// Set slots to end.
|
size_t end = interval->GetLastSibling()->GetEnd();
|
for (size_t s = slot; s < upper; s++) {
|
(*spill_slots)[s] = end;
|
}
|
|
// Note that the exact spill slot location will be computed when we resolve,
|
// that is when we know the number of spill slots for each type.
|
parent->SetSpillSlot(slot);
|
}
|
|
void RegisterAllocatorLinearScan::AllocateSpillSlotForCatchPhi(HPhi* phi) {
|
LiveInterval* interval = phi->GetLiveInterval();
|
|
HInstruction* previous_phi = phi->GetPrevious();
|
DCHECK(previous_phi == nullptr ||
|
previous_phi->AsPhi()->GetRegNumber() <= phi->GetRegNumber())
|
<< "Phis expected to be sorted by vreg number, so that equivalent phis are adjacent.";
|
|
if (phi->IsVRegEquivalentOf(previous_phi)) {
|
// This is an equivalent of the previous phi. We need to assign the same
|
// catch phi slot.
|
DCHECK(previous_phi->GetLiveInterval()->HasSpillSlot());
|
interval->SetSpillSlot(previous_phi->GetLiveInterval()->GetSpillSlot());
|
} else {
|
// Allocate a new spill slot for this catch phi.
|
// TODO: Reuse spill slots when intervals of phis from different catch
|
// blocks do not overlap.
|
interval->SetSpillSlot(catch_phi_spill_slots_);
|
catch_phi_spill_slots_ += interval->NumberOfSpillSlotsNeeded();
|
}
|
}
|
|
} // namespace art
|
