/*
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* Copyright (C) 2016 The Android Open Source Project
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#ifndef ART_COMPILER_DEBUG_ELF_DEBUG_LOC_WRITER_H_
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#define ART_COMPILER_DEBUG_ELF_DEBUG_LOC_WRITER_H_
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#include <cstring>
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#include <map>
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#include "arch/instruction_set.h"
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#include "compiled_method.h"
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#include "debug/method_debug_info.h"
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#include "dwarf/debug_info_entry_writer.h"
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#include "dwarf/register.h"
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#include "stack_map.h"
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namespace art {
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namespace debug {
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using Reg = dwarf::Reg;
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static Reg GetDwarfCoreReg(InstructionSet isa, int machine_reg) {
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switch (isa) {
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case InstructionSet::kArm:
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case InstructionSet::kThumb2:
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return Reg::ArmCore(machine_reg);
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case InstructionSet::kArm64:
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return Reg::Arm64Core(machine_reg);
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case InstructionSet::kX86:
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return Reg::X86Core(machine_reg);
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case InstructionSet::kX86_64:
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return Reg::X86_64Core(machine_reg);
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case InstructionSet::kMips:
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return Reg::MipsCore(machine_reg);
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case InstructionSet::kMips64:
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return Reg::Mips64Core(machine_reg);
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case InstructionSet::kNone:
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LOG(FATAL) << "No instruction set";
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}
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UNREACHABLE();
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}
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static Reg GetDwarfFpReg(InstructionSet isa, int machine_reg) {
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switch (isa) {
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case InstructionSet::kArm:
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case InstructionSet::kThumb2:
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return Reg::ArmFp(machine_reg);
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case InstructionSet::kArm64:
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return Reg::Arm64Fp(machine_reg);
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case InstructionSet::kX86:
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return Reg::X86Fp(machine_reg);
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case InstructionSet::kX86_64:
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return Reg::X86_64Fp(machine_reg);
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case InstructionSet::kMips:
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return Reg::MipsFp(machine_reg);
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case InstructionSet::kMips64:
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return Reg::Mips64Fp(machine_reg);
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case InstructionSet::kNone:
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LOG(FATAL) << "No instruction set";
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}
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UNREACHABLE();
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}
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struct VariableLocation {
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uint32_t low_pc; // Relative to compilation unit.
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uint32_t high_pc; // Relative to compilation unit.
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DexRegisterLocation reg_lo; // May be None if the location is unknown.
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DexRegisterLocation reg_hi; // Most significant bits of 64-bit value.
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};
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// Get the location of given dex register (e.g. stack or machine register).
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// Note that the location might be different based on the current pc.
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// The result will cover all ranges where the variable is in scope.
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// PCs corresponding to stackmap with dex register map are accurate,
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// all other PCs are best-effort only.
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static std::vector<VariableLocation> GetVariableLocations(
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const MethodDebugInfo* method_info,
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const std::vector<DexRegisterMap>& dex_register_maps,
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uint16_t vreg,
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bool is64bitValue,
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uint64_t compilation_unit_code_address,
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uint32_t dex_pc_low,
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uint32_t dex_pc_high,
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InstructionSet isa) {
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std::vector<VariableLocation> variable_locations;
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// Get stack maps sorted by pc (they might not be sorted internally).
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// TODO(dsrbecky) Remove this once stackmaps get sorted by pc.
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const CodeInfo code_info(method_info->code_info);
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std::map<uint32_t, uint32_t> stack_maps; // low_pc -> stack_map_index.
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for (uint32_t s = 0; s < code_info.GetNumberOfStackMaps(); s++) {
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StackMap stack_map = code_info.GetStackMapAt(s);
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DCHECK(stack_map.IsValid());
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if (!stack_map.HasDexRegisterMap()) {
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// The compiler creates stackmaps without register maps at the start of
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// basic blocks in order to keep instruction-accurate line number mapping.
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// However, we never stop at those (breakpoint locations always have map).
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// Therefore, for the purpose of local variables, we ignore them.
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// The main reason for this is to save space by avoiding undefined gaps.
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continue;
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}
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const uint32_t pc_offset = stack_map.GetNativePcOffset(isa);
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DCHECK_LE(pc_offset, method_info->code_size);
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DCHECK_LE(compilation_unit_code_address, method_info->code_address);
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const uint32_t low_pc = dchecked_integral_cast<uint32_t>(
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method_info->code_address + pc_offset - compilation_unit_code_address);
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stack_maps.emplace(low_pc, s);
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}
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// Create entries for the requested register based on stack map data.
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for (auto it = stack_maps.begin(); it != stack_maps.end(); it++) {
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const uint32_t low_pc = it->first;
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const uint32_t stack_map_index = it->second;
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const StackMap stack_map = code_info.GetStackMapAt(stack_map_index);
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auto next_it = it;
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next_it++;
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const uint32_t high_pc = next_it != stack_maps.end()
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? next_it->first
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: method_info->code_address + method_info->code_size - compilation_unit_code_address;
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DCHECK_LE(low_pc, high_pc);
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if (low_pc == high_pc) {
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continue; // Ignore if the address range is empty.
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}
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// Check that the stack map is in the requested range.
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uint32_t dex_pc = stack_map.GetDexPc();
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if (!(dex_pc_low <= dex_pc && dex_pc < dex_pc_high)) {
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// The variable is not in scope at this PC. Therefore omit the entry.
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// Note that this is different to None() entry which means in scope, but unknown location.
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continue;
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}
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// Find the location of the dex register.
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DexRegisterLocation reg_lo = DexRegisterLocation::None();
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DexRegisterLocation reg_hi = DexRegisterLocation::None();
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DCHECK_LT(stack_map_index, dex_register_maps.size());
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DexRegisterMap dex_register_map = dex_register_maps[stack_map_index];
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DCHECK(!dex_register_map.empty());
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CodeItemDataAccessor accessor(*method_info->dex_file, method_info->code_item);
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reg_lo = dex_register_map[vreg];
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if (is64bitValue) {
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reg_hi = dex_register_map[vreg + 1];
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}
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// Add location entry for this address range.
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if (!variable_locations.empty() &&
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variable_locations.back().reg_lo == reg_lo &&
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variable_locations.back().reg_hi == reg_hi &&
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variable_locations.back().high_pc == low_pc) {
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// Merge with the previous entry (extend its range).
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variable_locations.back().high_pc = high_pc;
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} else {
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variable_locations.push_back({low_pc, high_pc, reg_lo, reg_hi});
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}
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}
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return variable_locations;
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}
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// Write table into .debug_loc which describes location of dex register.
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// The dex register might be valid only at some points and it might
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// move between machine registers and stack.
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static void WriteDebugLocEntry(const MethodDebugInfo* method_info,
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const std::vector<DexRegisterMap>& dex_register_maps,
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uint16_t vreg,
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bool is64bitValue,
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uint64_t compilation_unit_code_address,
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uint32_t dex_pc_low,
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uint32_t dex_pc_high,
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InstructionSet isa,
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dwarf::DebugInfoEntryWriter<>* debug_info,
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std::vector<uint8_t>* debug_loc_buffer,
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std::vector<uint8_t>* debug_ranges_buffer) {
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using Kind = DexRegisterLocation::Kind;
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if (method_info->code_info == nullptr || dex_register_maps.empty()) {
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return;
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}
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std::vector<VariableLocation> variable_locations = GetVariableLocations(
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method_info,
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dex_register_maps,
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vreg,
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is64bitValue,
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compilation_unit_code_address,
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dex_pc_low,
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dex_pc_high,
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isa);
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// Write .debug_loc entries.
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dwarf::Writer<> debug_loc(debug_loc_buffer);
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const size_t debug_loc_offset = debug_loc.size();
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const bool is64bit = Is64BitInstructionSet(isa);
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std::vector<uint8_t> expr_buffer;
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for (const VariableLocation& variable_location : variable_locations) {
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// Translate dex register location to DWARF expression.
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// Note that 64-bit value might be split to two distinct locations.
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// (for example, two 32-bit machine registers, or even stack and register)
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dwarf::Expression expr(&expr_buffer);
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DexRegisterLocation reg_lo = variable_location.reg_lo;
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DexRegisterLocation reg_hi = variable_location.reg_hi;
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for (int piece = 0; piece < (is64bitValue ? 2 : 1); piece++) {
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DexRegisterLocation reg_loc = (piece == 0 ? reg_lo : reg_hi);
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const Kind kind = reg_loc.GetKind();
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const int32_t value = reg_loc.GetValue();
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if (kind == Kind::kInStack) {
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// The stack offset is relative to SP. Make it relative to CFA.
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expr.WriteOpFbreg(value - method_info->frame_size_in_bytes);
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if (piece == 0 && reg_hi.GetKind() == Kind::kInStack &&
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reg_hi.GetValue() == value + 4) {
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break; // the high word is correctly implied by the low word.
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}
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} else if (kind == Kind::kInRegister) {
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expr.WriteOpReg(GetDwarfCoreReg(isa, value).num());
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if (piece == 0 && reg_hi.GetKind() == Kind::kInRegisterHigh &&
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reg_hi.GetValue() == value) {
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break; // the high word is correctly implied by the low word.
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}
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} else if (kind == Kind::kInFpuRegister) {
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if ((isa == InstructionSet::kArm || isa == InstructionSet::kThumb2) &&
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piece == 0 && reg_hi.GetKind() == Kind::kInFpuRegister &&
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reg_hi.GetValue() == value + 1 && value % 2 == 0) {
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// Translate S register pair to D register (e.g. S4+S5 to D2).
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expr.WriteOpReg(Reg::ArmDp(value / 2).num());
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break;
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}
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expr.WriteOpReg(GetDwarfFpReg(isa, value).num());
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if (piece == 0 && reg_hi.GetKind() == Kind::kInFpuRegisterHigh &&
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reg_hi.GetValue() == reg_lo.GetValue()) {
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break; // the high word is correctly implied by the low word.
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}
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} else if (kind == Kind::kConstant) {
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expr.WriteOpConsts(value);
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expr.WriteOpStackValue();
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} else if (kind == Kind::kNone) {
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break;
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} else {
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// kInStackLargeOffset and kConstantLargeValue are hidden by GetKind().
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// kInRegisterHigh and kInFpuRegisterHigh should be handled by
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// the special cases above and they should not occur alone.
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LOG(WARNING) << "Unexpected register location: " << kind
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<< " (This can indicate either a bug in the dexer when generating"
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<< " local variable information, or a bug in ART compiler."
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<< " Please file a bug at go/art-bug)";
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break;
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}
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if (is64bitValue) {
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// Write the marker which is needed by split 64-bit values.
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// This code is skipped by the special cases.
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expr.WriteOpPiece(4);
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}
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}
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if (expr.size() > 0) {
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if (is64bit) {
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debug_loc.PushUint64(variable_location.low_pc);
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debug_loc.PushUint64(variable_location.high_pc);
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} else {
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debug_loc.PushUint32(variable_location.low_pc);
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debug_loc.PushUint32(variable_location.high_pc);
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}
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// Write the expression.
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debug_loc.PushUint16(expr.size());
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debug_loc.PushData(expr.data());
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} else {
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// Do not generate .debug_loc if the location is not known.
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}
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}
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// Write end-of-list entry.
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if (is64bit) {
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debug_loc.PushUint64(0);
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debug_loc.PushUint64(0);
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} else {
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debug_loc.PushUint32(0);
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debug_loc.PushUint32(0);
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}
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// Write .debug_ranges entries.
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// This includes ranges where the variable is in scope but the location is not known.
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dwarf::Writer<> debug_ranges(debug_ranges_buffer);
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size_t debug_ranges_offset = debug_ranges.size();
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for (size_t i = 0; i < variable_locations.size(); i++) {
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uint32_t low_pc = variable_locations[i].low_pc;
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uint32_t high_pc = variable_locations[i].high_pc;
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while (i + 1 < variable_locations.size() && variable_locations[i+1].low_pc == high_pc) {
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// Merge address range with the next entry.
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high_pc = variable_locations[++i].high_pc;
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}
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if (is64bit) {
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debug_ranges.PushUint64(low_pc);
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debug_ranges.PushUint64(high_pc);
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} else {
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debug_ranges.PushUint32(low_pc);
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debug_ranges.PushUint32(high_pc);
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}
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}
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// Write end-of-list entry.
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if (is64bit) {
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debug_ranges.PushUint64(0);
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debug_ranges.PushUint64(0);
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} else {
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debug_ranges.PushUint32(0);
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debug_ranges.PushUint32(0);
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}
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// Simple de-duplication - check whether this entry is same as the last one (or tail of it).
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size_t debug_ranges_entry_size = debug_ranges.size() - debug_ranges_offset;
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if (debug_ranges_offset >= debug_ranges_entry_size) {
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size_t previous_offset = debug_ranges_offset - debug_ranges_entry_size;
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if (memcmp(debug_ranges_buffer->data() + previous_offset,
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debug_ranges_buffer->data() + debug_ranges_offset,
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debug_ranges_entry_size) == 0) {
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// Remove what we have just written and use the last entry instead.
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debug_ranges_buffer->resize(debug_ranges_offset);
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debug_ranges_offset = previous_offset;
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}
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}
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// Write attributes to .debug_info.
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debug_info->WriteSecOffset(dwarf::DW_AT_location, debug_loc_offset);
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debug_info->WriteSecOffset(dwarf::DW_AT_start_scope, debug_ranges_offset);
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}
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} // namespace debug
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} // namespace art
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#endif // ART_COMPILER_DEBUG_ELF_DEBUG_LOC_WRITER_H_
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