/* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */
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/*
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* Copyright (C) 2018, STMicroelectronics - All Rights Reserved
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*/
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#ifndef __PMIC_STPMU1_H_
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#define __PMIC_STPMU1_H_
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#define STPMU1_MASK_RESET_BUCK 0x18
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#define STPMU1_BUCKX_CTRL_REG(buck) (0x20 + (buck))
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#define STPMU1_VREF_CTRL_REG 0x24
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#define STPMU1_LDOX_CTRL_REG(ldo) (0x25 + (ldo))
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#define STPMU1_USB_CTRL_REG 0x40
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#define STPMU1_NVM_USER_STATUS_REG 0xb8
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#define STPMU1_NVM_USER_CONTROL_REG 0xb9
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#define STPMU1_MASK_RESET_BUCK3 BIT(2)
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#define STPMU1_BUCK_EN BIT(0)
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#define STPMU1_BUCK_MODE BIT(1)
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#define STPMU1_BUCK_OUTPUT_MASK GENMASK(7, 2)
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#define STPMU1_BUCK_OUTPUT_SHIFT 2
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#define STPMU1_BUCK2_1200000V (24 << STPMU1_BUCK_OUTPUT_SHIFT)
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#define STPMU1_BUCK2_1350000V (30 << STPMU1_BUCK_OUTPUT_SHIFT)
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#define STPMU1_BUCK3_1800000V (39 << STPMU1_BUCK_OUTPUT_SHIFT)
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#define STPMU1_VREF_EN BIT(0)
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#define STPMU1_LDO_EN BIT(0)
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#define STPMU1_LDO12356_OUTPUT_MASK GENMASK(6, 2)
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#define STPMU1_LDO12356_OUTPUT_SHIFT 2
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#define STPMU1_LDO3_MODE BIT(7)
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#define STPMU1_LDO3_DDR_SEL 31
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#define STPMU1_LDO3_1800000 (9 << STPMU1_LDO12356_OUTPUT_SHIFT)
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#define STPMU1_LDO4_UV 3300000
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#define STPMU1_USB_BOOST_EN BIT(0)
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#define STPMU1_USB_PWR_SW_EN GENMASK(2, 1)
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#define STPMU1_NVM_USER_CONTROL_PROGRAM BIT(0)
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#define STPMU1_NVM_USER_CONTROL_READ BIT(1)
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#define STPMU1_NVM_USER_STATUS_BUSY BIT(0)
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#define STPMU1_NVM_USER_STATUS_ERROR BIT(1)
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#define STPMU1_DEFAULT_START_UP_DELAY_MS 1
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#define STPMU1_USB_BOOST_START_UP_DELAY_MS 10
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enum {
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STPMU1_BUCK1,
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STPMU1_BUCK2,
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STPMU1_BUCK3,
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STPMU1_BUCK4,
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STPMU1_MAX_BUCK,
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};
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enum {
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STPMU1_BUCK_MODE_HP,
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STPMU1_BUCK_MODE_LP,
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};
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enum {
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STPMU1_LDO1,
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STPMU1_LDO2,
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STPMU1_LDO3,
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STPMU1_LDO4,
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STPMU1_LDO5,
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STPMU1_LDO6,
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STPMU1_MAX_LDO,
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};
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enum {
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STPMU1_LDO_MODE_NORMAL,
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STPMU1_LDO_MODE_BYPASS,
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STPMU1_LDO_MODE_SINK_SOURCE,
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};
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enum {
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STPMU1_PWR_SW1,
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STPMU1_PWR_SW2,
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STPMU1_MAX_PWR_SW,
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};
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#endif
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