/*
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* SUNXI WakeupGen Source file
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*
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* SUNXI WakeupGen is the interrupt controller extension used along
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* with ARM GIC to wake the CPU out from low power states on
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* external interrupts. It is responsible for generating wakeup
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* event from the incoming interrupts and enable bits. It is
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* implemented in PMU always ON power domain. During normal operation,
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* WakeupGen delivers external interrupts directly to the GIC.
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*
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* Copyright (C) 2017 Allwinner Technology, Inc.
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* fanqinghua <fanqinghua@allwinnertech.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/irq.h>
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#include <linux/irqchip.h>
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#include <linux/irqdomain.h>
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#include <linux/of_address.h>
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#include <linux/platform_device.h>
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#include <linux/cpu.h>
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#include <linux/notifier.h>
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#include <linux/cpu_pm.h>
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#include <linux/arisc/arisc.h>
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#define GIC_SUPPORT_IRQS 1024
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static int sunxi_irq_set_wake(struct irq_data *d, unsigned int on)
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{
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if (on)
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arisc_set_wakeup_source(SET_ROOT_WAKEUP_SOURCE(d->hwirq));
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else
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arisc_clear_wakeup_source(SET_ROOT_WAKEUP_SOURCE(d->hwirq));
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/*
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* Do *not* call into the parent, as the GIC doesn't have any
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* wake-up facility...
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*/
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return 0;
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}
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static struct irq_chip wakeupgen_chip = {
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.name = "wakeupgen",
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.irq_enable = irq_chip_enable_parent,
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.irq_disable = irq_chip_disable_parent,
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.irq_eoi = irq_chip_eoi_parent,
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.irq_mask = irq_chip_mask_parent,
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.irq_unmask = irq_chip_unmask_parent,
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.irq_retrigger = irq_chip_retrigger_hierarchy,
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.irq_set_wake = sunxi_irq_set_wake,
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.irq_set_type = irq_chip_set_type_parent,
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#ifdef CONFIG_SMP
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.irq_set_affinity = irq_chip_set_affinity_parent,
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#endif
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};
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static int sunxi_domain_translate(struct irq_domain *d,
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struct irq_fwspec *fwspec,
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unsigned long *hwirq,
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unsigned int *type)
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{
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if (is_of_node(fwspec->fwnode)) {
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if (fwspec->param_count != 3)
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return -EINVAL;
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/* No PPI should point to this domain */
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if (fwspec->param[0] != 0)
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return -EINVAL;
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*hwirq = fwspec->param[1];
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*type = fwspec->param[2];
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return 0;
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}
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return -EINVAL;
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}
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static int sunxi_domain_alloc(struct irq_domain *domain,
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unsigned int irq,
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unsigned int nr_irqs, void *data)
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{
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struct irq_fwspec *fwspec = data;
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struct irq_fwspec parent_fwspec;
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irq_hw_number_t hwirq;
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int i;
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if (fwspec->param_count != 3)
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return -EINVAL; /* Not GIC compliant */
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if (fwspec->param[0] != 0)
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return -EINVAL; /* No PPI should point to this domain */
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hwirq = fwspec->param[1];
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if (hwirq >= GIC_SUPPORT_IRQS)
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return -EINVAL; /* Can't deal with this */
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for (i = 0; i < nr_irqs; i++)
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irq_domain_set_hwirq_and_chip(domain, irq + i, hwirq + i,
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&wakeupgen_chip, NULL);
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parent_fwspec = *fwspec;
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parent_fwspec.fwnode = domain->parent->fwnode;
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return irq_domain_alloc_irqs_parent(domain, irq, nr_irqs,
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&parent_fwspec);
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}
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static const struct irq_domain_ops sunxi_domain_ops = {
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.translate = sunxi_domain_translate,
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.alloc = sunxi_domain_alloc,
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.free = irq_domain_free_irqs_common,
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};
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static int __init wakeupgen_init(struct device_node *node,
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struct device_node *parent)
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{
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struct irq_domain *parent_domain, *domain;
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if (!parent) {
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pr_err("%s: no parent, giving up\n", node->full_name);
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return -ENODEV;
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}
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parent_domain = irq_find_host(parent);
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if (!parent_domain) {
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pr_err("%s: unable to obtain parent domain\n", node->full_name);
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return -ENXIO;
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}
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domain = irq_domain_add_hierarchy(parent_domain, 0, GIC_SUPPORT_IRQS,
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node, &sunxi_domain_ops,
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NULL);
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if (!domain) {
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pr_err("%s: failed to allocated domain\n", node->full_name);
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return -ENOMEM;
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}
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return 0;
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}
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IRQCHIP_DECLARE(sunxi_wakeupgen, "allwinner,sunxi-wakeupgen", wakeupgen_init);
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