/*
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* drivers/spi/spi-sunxi.h
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*
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* Copyright (C) 2012 - 2016 Reuuimlla Limited
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* Pan Nan <pannan@reuuimllatech.com>
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*
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* SUNXI SPI Register Definition
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* 2013.5.7 Mintow <duanmintao@allwinnertech.com>
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* Adapt to support sun8i/sun9i of Allwinner.
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*/
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#include <linux/regulator/consumer.h>
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#ifndef _SUNXI_SPI_H_
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#define _SUNXI_SPI_H_
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#define HEXADECIMAL (0x10)
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#define REG_END (0x0f)
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#define SAMPLE_NUMBER (0x80)
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#define REG_INTERVAL (0x04)
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#define REG_CL (0x0c)
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#define SPI_MODULE_NUM (4)
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#define SPI_FIFO_DEPTH (128)
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#define MAX_FIFU 64
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#define BULK_DATA_BOUNDARY 64 /* can modify to adapt the application */
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#define SPI_MAX_FREQUENCY 100000000 /* spi controller just support 100Mhz */
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#define SPI_HIGH_FREQUENCY 60000000 /* sample mode threshold frequency */
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#define SPI_LOW_FREQUENCY 24000000 /* sample mode threshold frequency */
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/* SPI Registers offsets from peripheral base address */
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#define SPI_VER_REG (0x00) /* version number register */
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#define SPI_GC_REG (0x04) /* global control register */
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#define SPI_TC_REG (0x08) /* transfer control register */
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#define SPI_INT_CTL_REG (0x10) /* interrupt control register */
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#define SPI_INT_STA_REG (0x14) /* interrupt status register */
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#define SPI_FIFO_CTL_REG (0x18) /* fifo control register */
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#define SPI_FIFO_STA_REG (0x1C) /* fifo status register */
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#define SPI_WAIT_CNT_REG (0x20) /* wait clock counter register */
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#define SPI_CLK_CTL_REG (0x24) /* clock rate control register */
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#define SPI_BURST_CNT_REG (0x30) /* burst counter register */
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#define SPI_TRANSMIT_CNT_REG (0x34) /* transmit counter register */
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#define SPI_BCC_REG (0x38) /* burst control counter register */
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#define SPI_DMA_CTL_REG (0x88) /* DMA control register, only for 1639 */
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#define SPI_TXDATA_REG (0x200) /* tx data register */
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#define SPI_RXDATA_REG (0x300) /* rx data register */
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/* SPI Global Control Register Bit Fields & Masks,default value:0x0000_0080 */
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#define SPI_GC_EN (0x1 << 0) /* SPI module enable control 1:enable; 0:disable; default:0 */
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#define SPI_GC_MODE (0x1 << 1) /* SPI function mode select 1:master; 0:slave; default:0 */
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#define SPI_GC_TP_EN (0x1 << 7) /* SPI transmit stop enable 1:stop transmit data when RXFIFO is full; 0:ignore RXFIFO status; default:1 */
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#define SPI_GC_SRST (0x1 << 31) /* soft reset, write 1 will clear SPI control, auto clear to 0 */
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/* SPI Transfer Control Register Bit Fields & Masks,default value:0x0000_0087 */
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#define SPI_TC_PHA (0x1 << 0) /* SPI Clock/Data phase control,0: phase0,1: phase1;default:1 */
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#define SPI_TC_POL (0x1 << 1) /* SPI Clock polarity control,0:low level idle,1:high level idle;default:1 */
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#define SPI_TC_SPOL (0x1 << 2) /* SPI Chip select signal polarity control,default: 1,low effective like this:~~|_____~~ */
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#define SPI_TC_SSCTL (0x1 << 3) /* SPI chip select control,default 0:SPI_SSx remains asserted between SPI bursts,1:negate SPI_SSx between SPI bursts */
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#define SPI_TC_SS_MASK (0x3 << 4) /* SPI chip select:00-SPI_SS0;01-SPI_SS1;10-SPI_SS2;11-SPI_SS3*/
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#define SPI_TC_SS_OWNER (0x1 << 6) /* SS output mode select default is 0:automatic output SS;1:manual output SS */
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#define SPI_TC_SS_LEVEL (0x1 << 7) /* defautl is 1:set SS to high;0:set SS to low */
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#define SPI_TC_DHB (0x1 << 8) /* Discard Hash Burst,default 0:receiving all spi burst in BC period 1:discard unused,fectch WTC bursts */
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#define SPI_TC_DDB (0x1 << 9) /* Dummy burst Type,default 0: dummy spi burst is zero;1:dummy spi burst is one */
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#define SPI_TC_RPSM (0x1 << 10) /* select mode for high speed write,0:normal write mode,1:rapids write mode,default 0 */
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#define SPI_TC_SDM (0x1 << 13) /* master sample data mode, 1: normal sample mode;0:delay sample mode. */
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#define SPI_TC_SDC (0x1 << 11) /* master sample data control, 1: delay--high speed operation;0:no delay. */
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#define SPI_TC_FBS (0x1 << 12) /* LSB/MSB transfer first select 0:MSB,1:LSB,default 0:MSB first */
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#define SPI_TC_XCH (0x1 << 31) /* Exchange burst default 0:idle,1:start exchange;when BC is zero,this bit cleared by SPI controller*/
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#define SPI_TC_SS_BIT_POS (4)
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/* SPI Interrupt Control Register Bit Fields & Masks,default value:0x0000_0000 */
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#define SPI_INTEN_RX_RDY (0x1 << 0) /* rxFIFO Ready Interrupt Enable,---used for immediately received,0:disable;1:enable */
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#define SPI_INTEN_RX_EMP (0x1 << 1) /* rxFIFO Empty Interrupt Enable ---used for IRQ received */
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#define SPI_INTEN_RX_FULL (0x1 << 2) /* rxFIFO Full Interrupt Enable ---seldom used */
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#define SPI_INTEN_TX_ERQ (0x1 << 4) /* txFIFO Empty Request Interrupt Enable ---seldom used */
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#define SPI_INTEN_TX_EMP (0x1 << 5) /* txFIFO Empty Interrupt Enable ---used for IRQ tx */
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#define SPI_INTEN_TX_FULL (0x1 << 6) /* txFIFO Full Interrupt Enable ---seldom used */
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#define SPI_INTEN_RX_OVF (0x1 << 8) /* rxFIFO Overflow Interrupt Enable ---used for error detect */
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#define SPI_INTEN_RX_UDR (0x1 << 9) /* rxFIFO Underrun Interrupt Enable ---used for error detect */
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#define SPI_INTEN_TX_OVF (0x1 << 10) /* txFIFO Overflow Interrupt Enable ---used for error detect */
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#define SPI_INTEN_TX_UDR (0x1 << 11) /* txFIFO Underrun Interrupt Enable ---not happened */
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#define SPI_INTEN_TC (0x1 << 12) /* Transfer Completed Interrupt Enable ---used */
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#define SPI_INTEN_SSI (0x1 << 13) /* SSI interrupt Enable,chip select from valid state to invalid state,for slave used only */
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#define SPI_INTEN_ERR (SPI_INTEN_TX_OVF|SPI_INTEN_RX_UDR|SPI_INTEN_RX_OVF) /* NO txFIFO underrun */
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#define SPI_INTEN_MASK (0x77|(0x3f<<8))
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/* SPI Interrupt Status Register Bit Fields & Masks,default value:0x0000_0022 */
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#define SPI_INT_STA_RX_RDY (0x1 << 0) /* rxFIFO ready, 0:RX_WL < RX_TRIG_LEVEL,1:RX_WL >= RX_TRIG_LEVEL */
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#define SPI_INT_STA_RX_EMP (0x1 << 1) /* rxFIFO empty, this bit is set when rxFIFO is empty */
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#define SPI_INT_STA_RX_FULL (0x1 << 2) /* rxFIFO full, this bit is set when rxFIFO is full */
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#define SPI_INT_STA_TX_RDY (0x1 << 4) /* txFIFO ready, 0:TX_WL > TX_TRIG_LEVEL,1:TX_WL <= TX_TRIG_LEVEL */
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#define SPI_INT_STA_TX_EMP (0x1 << 5) /* txFIFO empty, this bit is set when txFIFO is empty */
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#define SPI_INT_STA_TX_FULL (0x1 << 6) /* txFIFO full, this bit is set when txFIFO is full */
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#define SPI_INT_STA_RX_OVF (0x1 << 8) /* rxFIFO overflow, when set rxFIFO has overflowed */
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#define SPI_INT_STA_RX_UDR (0x1 << 9) /* rxFIFO underrun, when set rxFIFO has underrun */
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#define SPI_INT_STA_TX_OVF (0x1 << 10) /* txFIFO overflow, when set txFIFO has overflowed */
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#define SPI_INT_STA_TX_UDR (0x1 << 11) /* fxFIFO underrun, when set txFIFO has underrun */
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#define SPI_INT_STA_TC (0x1 << 12) /* Transfer Completed */
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#define SPI_INT_STA_SSI (0x1 << 13) /* SS invalid interrupt, when set SS has changed from valid to invalid */
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#define SPI_INT_STA_ERR (SPI_INT_STA_TX_OVF|SPI_INT_STA_RX_UDR|SPI_INT_STA_RX_OVF) /* NO txFIFO underrun */
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#define SPI_INT_STA_MASK (0x77|(0x3f<<8))
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/* SPI FIFO Control Register Bit Fields & Masks,default value:0x0040_0001 */
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#define SPI_FIFO_CTL_RX_LEVEL (0xFF << 0) /* rxFIFO reday request trigger level,default 0x1 */
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#define SPI_FIFO_CTL_RX_DRQEN (0x1 << 8) /* rxFIFO DMA request enable,1:enable,0:disable */
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#define SPI_FIFO_CTL_RX_TESTEN (0x1 << 14) /* rxFIFO test mode enable,1:enable,0:disable */
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#define SPI_FIFO_CTL_RX_RST (0x1 << 15) /* rxFIFO reset, write 1, auto clear to 0 */
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#define SPI_FIFO_CTL_TX_LEVEL (0xFF << 16) /* txFIFO empty request trigger level,default 0x40 */
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#define SPI_FIFO_CTL_TX_DRQEN (0x1 << 24) /* txFIFO DMA request enable,1:enable,0:disable */
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#define SPI_FIFO_CTL_TX_TESTEN (0x1 << 30) /* txFIFO test mode enable,1:enable,0:disable */
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#define SPI_FIFO_CTL_TX_RST (0x1 << 31) /* txFIFO reset, write 1, auto clear to 0 */
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#define SPI_FIFO_CTL_DRQEN_MASK (SPI_FIFO_CTL_TX_DRQEN|SPI_FIFO_CTL_RX_DRQEN)
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/* SPI FIFO Status Register Bit Fields & Masks,default value:0x0000_0000 */
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#define SPI_FIFO_STA_RX_CNT (0xFF << 0) /* rxFIFO counter,how many bytes in rxFIFO */
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#define SPI_FIFO_STA_RB_CNT (0x7 << 12) /* rxFIFO read buffer counter,how many bytes in rxFIFO read buffer */
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#define SPI_FIFO_STA_RB_WR (0x1 << 15) /* rxFIFO read buffer write enable */
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#define SPI_FIFO_STA_TX_CNT (0xFF << 16) /* txFIFO counter,how many bytes in txFIFO */
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#define SPI_FIFO_STA_TB_CNT (0x7 << 28) /* txFIFO write buffer counter,how many bytes in txFIFO write buffer */
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#define SPI_FIFO_STA_TB_WR (0x1 << 31) /* txFIFO write buffer write enable */
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#define SPI_RXCNT_BIT_POS (0)
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#define SPI_TXCNT_BIT_POS (16)
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/* SPI Wait Clock Register Bit Fields & Masks,default value:0x0000_0000 */
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#define SPI_WAIT_WCC_MASK (0xFFFF << 0) /* used only in master mode: Wait Between Transactions */
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#define SPI_WAIT_SWC_MASK (0xF << 16) /* used only in master mode: Wait before start dual data transfer in dual SPI mode */
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/* SPI Clock Control Register Bit Fields & Masks,default:0x0000_0002 */
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#define SPI_CLK_CTL_CDR2 (0xFF << 0) /* Clock Divide Rate 2,master mode only : SPI_CLK = AHB_CLK/(2*(n+1)) */
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#define SPI_CLK_CTL_CDR1 (0xF << 8) /* Clock Divide Rate 1,master mode only : SPI_CLK = AHB_CLK/2^n */
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#define SPI_CLK_CTL_DRS (0x1 << 12) /* Divide rate select,default,0:rate 1;1:rate 2 */
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#define SPI_CLK_SCOPE (SPI_CLK_CTL_CDR2+1)
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/* SPI Master Burst Counter Register Bit Fields & Masks,default:0x0000_0000 */
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/* master mode: when SMC = 1,BC specifies total burst number, Max length is 16Mbytes */
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#define SPI_BC_CNT_MASK (0xFFFFFF << 0) /* Total Burst Counter, tx length + rx length ,SMC=1 */
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/* SPI Master Transmit Counter reigster default:0x0000_0000 */
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#define SPI_TC_CNT_MASK (0xFFFFFF << 0) /* Write Transmit Counter, tx length, NOT rx length!!! */
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/* SPI Master Burst Control Counter reigster Bit Fields & Masks,default:0x0000_0000 */
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#define SPI_BCC_STC_MASK (0xFFFFFF << 0) /* master single mode transmit counter */
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#define SPI_BCC_DBC_MASK (0xF << 24) /* master dummy burst counter */
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#define SPI_BCC_DUAL_MODE (0x1 << 28) /* master dual mode RX enable */
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#define SPI_BCC_QUAD_MODE (0x1 << 29) /* master quad mode RX enable */
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#define SPI_PHA_ACTIVE_ (0x01)
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#define SPI_POL_ACTIVE_ (0x02)
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#define SPI_MODE_0_ACTIVE_ (0|0)
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#define SPI_MODE_1_ACTIVE_ (0|SPI_PHA_ACTIVE_)
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#define SPI_MODE_2_ACTIVE_ (SPI_POL_ACTIVE_|0)
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#define SPI_MODE_3_ACTIVE_ (SPI_POL_ACTIVE_|SPI_PHA_ACTIVE_)
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#define SPI_CS_HIGH_ACTIVE_ (0x04)
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#define SPI_LSB_FIRST_ACTIVE_ (0x08)
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#define SPI_DUMMY_ONE_ACTIVE_ (0x10)
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#define SPI_RECEIVE_ALL_ACTIVE_ (0x20)
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/* About SUNXI */
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#define SUNXI_SPI_DEV_NAME "spi"
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#define SUNXI_SPI_DRQ_RX(ch) (DRQSRC_SPI0_RX + ch)
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#define SUNXI_SPI_DRQ_TX(ch) (DRQDST_SPI0_TX + ch)
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/* About DMA */
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#ifdef CONFIG_ARCH_SUN9IW1P1
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#define SPI_DMA_WAIT_MODE 0xA5
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#define SPI_DMA_SHAKE_MODE 0xEA
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#define spi_set_dma_mode(base) writel(SPI_DMA_SHAKE_MODE, base + SPI_DMA_CTL_REG)
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#else
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#define spi_set_dma_mode(base)
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#endif
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struct sunxi_spi_platform_data {
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int cs_bitmap; /* cs0-0x1,cs1-0x2,cs0&cs1-0x3 */
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int cs_num; /* number of cs */
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char regulator_id[16];
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struct regulator *regulator;
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};
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/* spi device controller state, alloc */
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struct sunxi_spi_config {
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int bits_per_word; /* 8bit */
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int max_speed_hz; /* 80MHz */
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int mode; /* pha,pol,LSB,etc.. */
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};
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/* spi device data, used in dual spi mode */
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struct sunxi_dual_mode_dev_data {
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int dual_mode; /* dual SPI mode, 0-single mode, 1-dual mode */
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int single_cnt; /* single mode transmit counter */
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int dummy_cnt; /* dummy counter should be sent before receive in dual mode */
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};
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enum {
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DEBUG_INIT = 1U << 0,
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DEBUG_SUSPEND = 1U << 1,
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DEBUG_DATA = 1U << 2,
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DEBUG_INFO = 1U << 3,
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DEBUG_INFO1 = 1U << 4,
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DEBUG_INFO2 = 1U << 5,
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DEBUG_INFO3 = 1U << 6,
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DEBUG_INFO4 = 1U << 7,
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};
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#endif
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