/*
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* drivers/devfreq/dramfreq/sunxi_dramfreq.h
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*
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* Copyright(c) 2013-2015 Allwinnertech Co., Ltd.
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*
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* Author: Pan Nan <pannan@allwinnertech.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*/
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#ifndef __SUNXI_DRAMFREQ_H__
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#define __SUNXI_DRAMFREQ_H__
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#if defined(CONFIG_ARCH_SUN50IW3)
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#define SUNXI_DRAMFREQ_NORMAL (552000)
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#else
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#define SUNXI_DRAMFREQ_NORMAL (300000)
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#endif
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#define SUNXI_DRAMFREQ_IDLE (168000)
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#if defined(CONFIG_ARCH_SUN50IW3) || defined(CONFIG_ARCH_SUN50IW6)
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#if defined(CONFIG_ARCH_SUN50IW6)
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#define SUNXI_DRAM_FREQ_GOVERNOR "performance"
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#else
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#define SUNXI_DRAM_FREQ_GOVERNOR "adaptive"
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#endif
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/* Master reg number depend on platform */
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#define MASTER_REG_NUM 2
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/* Dramc Common register define */
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#define MC_WORK_MODE (0x000)
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#define MC_TIME_MEASUREMENT (0x00c)
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#define MC_MDFSCR (0x100)
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#define MC_MDFSMRMR (0x108)
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#define MDFS_BWC_PRD (0x114)
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#define MDFS_MASTER_ENABLE(x) (0x130 + 0x4 * (x))
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#define MDFS_MASTER_ENABLE0 (0x130)
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#define MDFS_MASTER_ENABLE1 (0x134)
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#define MDFS_IRQ_ACCESS_STATUS(x) (0x140 + 0x4 * (x))
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#define MDFS_IRQ_ACCESS_STATUS0 (0x140)
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#define MDFS_IRQ_ACCESS_STATUS1 (0x144)
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#define MDFS_IRQ_IDLE_STATUS(x) (0x148 + 0x4 * (x))
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#define MDFS_IRQ_IDLE_STATUS0 (0x148)
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#define MDFS_IRQ_IDLE_STATUS1 (0x14C)
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#define MDFS_IRQ_ACCESS_MASK_STA(x) (0x150 + 0x4 * (x))
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#define MDFS_IRQ_ACCESS_MASK_STA0 (0x150)
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#define MDFS_IRQ_ACCESS_MASK_STA1 (0x154)
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#define MDFS_IRQ_IDLE_MASK_STA(x) (0x158 + 0x4 * (x))
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#define MDFS_IRQ_IDLE_MASK_STA0 (0x158)
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#define MDFS_IRQ_IDLE_MASK_STA1 (0x15C)
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/* Dram Controller register define */
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#define PTR2 (0x04c)
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#define RFSHTMG (0x090)
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#define RFSHCTL1 (0x094)
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#define VTFCR (0x0b8)
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#define PGCR0 (0x100)
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#define ODTMAP (0x120)
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#define DXnGCR0(x) (0x344 + 0x80 * (x))
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/* CCMU register define */
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#define CCM_PLL_DDR1_REG (0x18)
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#define CCM_DRAM_CFG_REG (0x800)
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/* CCMU register define */
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#define CCM_DRAM_CFG_REG_PLL0_1_BIT (24)
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#else
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#define SUNXI_DRAM_FREQ_GOVERNOR "adaptive"
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/* Master reg number depend on platform */
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#define MASTER_REG_NUM 1
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/* Dramc Common register define */
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#define MC_WORK_MODE (0x000)
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#define MC_TIME_MEASUREMENT (0x00c)
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#define MC_MDFSCR (0x100)
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#define MC_MDFSMRMR (0x108)
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#define MDFS_IRQ_ACCESS_STATUS(x) (0x114 + 0x4 * (x))
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#define MDFS_IRQ_ACCESS_STATUS0 (0x114)
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#define MDFS_IRQ_IDLE_STATUS(x) (0x118 + 0x4 * (x))
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#define MDFS_IRQ_IDLE_STATUS0 (0x118)
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#define MDFS_IRQ_ACCESS_MASK_STA(x) (0x11C + 0x4 * (x))
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#define MDFS_IRQ_ACCESS_MASK_STA0 (0x11C)
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#define MDFS_IRQ_IDLE_MASK_STA(x) (0x120 + 0x4 * (x))
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#define MDFS_IRQ_IDLE_MASK_STA0 (0x120)
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#define MDFS_BWC_PRD (0x124)
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#define MDFS_MASTER_ENABLE(x) (0x134 + 0x4 * (x))
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#define MDFS_MASTER_ENABLE0 (0x134)
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#define MDFS_MASTER_STATUS (0x138)
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/* Dram Controller register define */
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#define PTR2 (0x04c)
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#define RFSHTMG (0x090)
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#define VTFCR (0x0b8)
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#define PGCR0 (0x100)
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#define ODTMAP (0x120)
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#define DXnGCR0(x) (0x344 + 0x80 * (x))
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/* CCMU register define */
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#define CCM_PLL_DDR1_REG (0x4C)
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#define CCM_DRAM_CFG_REG (0xF4)
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/* CCMU register define */
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#define CCM_DRAM_CFG_REG_PLL0_1_BIT (20)
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#endif
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#if defined(CONFIG_ARCH_SUN50I)
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#if defined(CONFIG_ARCH_SUN50IW6)
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enum DRAM_KEY_MASTER {
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MASTER_NULL,
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MASTER_GPU,
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MASTER_CSI,
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MASTER_DE,
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MASTER_MAX,
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};
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#elif defined(CONFIG_ARCH_SUN50IW3)
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enum DRAM_KEY_MASTER {
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MASTER_GPU,
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MASTER_VE,
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MASTER_DE,
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MASTER_MAX,
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};
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#else
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enum DRAM_KEY_MASTER {
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MASTER_GPU,
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MASTER_CSI,
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MASTER_DE,
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MASTER_MAX,
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};
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#endif
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#elif defined(CONFIG_ARCH_SUN8IW10)
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enum DRAM_KEY_MASTER {
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#ifdef CONFIG_EINK_PANEL_USED
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MASTER_EINK0,
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MASTER_EDMA,
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MASTER_EINK1,
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#else
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MASTER_DE,
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#endif
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MASTER_CSI,
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MASTER_MAX,
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};
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#elif defined(CONFIG_ARCH_SUN8IW11)
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enum DRAM_KEY_MASTER {
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MASTER_GPU,
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MASTER_CSI,
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MASTER_DE,
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MASTER_MAX,
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};
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#endif
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enum DRAM_FREQ_LEVEL {
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LV_0,
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LV_1,
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LV_2,
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LV_3,
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LV_4,
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LV_END,
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};
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enum DRAM_FREQ_TREND {
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FREQ_DOWN,
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FREQ_UP,
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};
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enum DRAM_MDFS_MODE {
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DFS_MODE,
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CFS_MODE,
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};
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enum GOVERNOR_STATE {
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STATE_INIT,
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STATE_EXIT,
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STATE_RUNNING,
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STATE_PAUSE,
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};
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struct dram_para_t {
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unsigned int dram_clk;
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unsigned int dram_type;
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unsigned int dram_zq;
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unsigned int dram_odt_en;
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unsigned int dram_para1;
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unsigned int dram_para2;
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unsigned int dram_mr0;
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unsigned int dram_mr1;
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unsigned int dram_mr2;
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unsigned int dram_mr3;
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unsigned int dram_tpr0;
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unsigned int dram_tpr1;
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unsigned int dram_tpr2;
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unsigned int dram_tpr3;
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unsigned int dram_tpr4;
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unsigned int dram_tpr5;
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unsigned int dram_tpr6;
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unsigned int dram_tpr7;
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unsigned int dram_tpr8;
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unsigned int dram_tpr9;
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unsigned int dram_tpr10;
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unsigned int dram_tpr11;
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unsigned int dram_tpr12;
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unsigned int dram_tpr13;
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};
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struct sunxi_dramfreq {
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unsigned int max;
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unsigned int min;
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#ifndef CONFIG_DEVFREQ_DRAM_FREQ_WITH_SOFT_NOTIFY
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unsigned int irq;
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unsigned int irq_access_status[MASTER_REG_NUM];
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unsigned int irq_idle_status[MASTER_REG_NUM];
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unsigned int irq_access_mask_sta[MASTER_REG_NUM];
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unsigned int irq_idle_mask_sta[MASTER_REG_NUM];
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#endif
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unsigned int pause;
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unsigned int key_masters[MASTER_MAX];
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enum DRAM_MDFS_MODE mode;
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#ifdef CONFIG_DEBUG_FS
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s64 dramfreq_set_us;
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s64 dramfreq_get_us;
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#endif
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struct mutex lock;
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spinlock_t master_lock;
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struct dram_para_t dram_para;
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unsigned int master_reg_num;
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struct devfreq *devfreq;
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void __iomem *dramcom_base;
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void __iomem *dramctl_base;
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void __iomem *ccu_base;
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struct clk *clk_pll_ddr0;
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struct clk *clk_pll_ddr1;
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int (*governor_state_update)(char *name, enum GOVERNOR_STATE);
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};
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extern struct sunxi_dramfreq *dramfreq;
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extern unsigned long dramfreq_get(void);
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#ifdef CONFIG_DEVFREQ_DRAM_FREQ_WITH_SOFT_NOTIFY
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extern int dramfreq_master_access(enum DRAM_KEY_MASTER master, bool access);
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#endif
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#endif /* __SUNXI_DRAMFREQ_H__ */
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