/*
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* Allwinner SoCs display driver.
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*
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* Copyright (C) 2016 Allwinner.
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include "de_clock.h"
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static void __iomem *de_base;
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#if defined(CONFIG_INDEPENDENT_DE)
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static void __iomem *de1_base;
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#endif
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static struct de_clk_para de_clk_tbl[] = {
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{
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.clk_no = DE_CLK_CORE0,
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.div = 1,
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.ahb_gate_adr = 0x04,
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.ahb_gate_shift = 0,
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.ahb_reset_adr = 0x08,
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.ahb_reset_shift = 0,
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.dram_gate_adr = 0x00,
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.dram_gate_shift = 32,
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.mod_adr = 0x00,
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.mod_enable_shift = 0,
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.mod_div_adr = 0x0c,
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.mod_div_shift = 0,
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.mod_div_width = 4,
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},
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{
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.clk_no = DE_CLK_CORE1,
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.div = 1,
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.ahb_gate_adr = 0x04,
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#if defined(CONFIG_INDEPENDENT_DE)
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.ahb_gate_shift = 0,
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#else
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.ahb_gate_shift = 1,
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#endif
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.ahb_reset_adr = 0x08,
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#if defined(CONFIG_INDEPENDENT_DE)
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.ahb_reset_shift = 0,
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#else
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#if defined(DE_WB_RESET_SHARE)
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.ahb_reset_shift = 2,
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#else
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.ahb_reset_shift = 1,
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#endif
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#endif
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.dram_gate_adr = 0x00,
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.dram_gate_shift = 32,
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.mod_adr = 0x00,
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#if defined(CONFIG_INDEPENDENT_DE)
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.mod_enable_shift = 0,
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#else
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.mod_enable_shift = 1,
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#endif
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.mod_div_adr = 0x0c,
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.mod_div_shift = 4,
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.mod_div_width = 4,
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},
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{
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.clk_no = DE_CLK_WB,
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.div = 1,
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.ahb_gate_adr = 0x04,
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.ahb_gate_shift = 2,
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.ahb_reset_adr = 0x08,
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.ahb_reset_shift = 2,
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.dram_gate_adr = 0x00,
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.dram_gate_shift = 32,
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.mod_adr = 0x00,
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.mod_enable_shift = 2,
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.mod_div_adr = 0x0c,
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.mod_div_shift = 8,
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.mod_div_width = 4,
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},
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};
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static s32 de_clk_set_div(u32 clk_no, u32 div)
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{
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u32 i = 0;
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u32 reg_val;
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u32 len = sizeof(de_clk_tbl) / sizeof(struct de_clk_para);
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#if defined(CONFIG_INDEPENDENT_DE)
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for (i = 0; i < len; i++) {
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if (de_clk_tbl[i].clk_no == clk_no) {
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reg_val = readl(de_clk_tbl[i].mod_div_adr + de1_base);
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reg_val =
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SET_BITS(de_clk_tbl[i].mod_div_shift,
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de_clk_tbl[i].mod_div_width, reg_val,
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(div - 1));
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writel(reg_val, de_clk_tbl[i].mod_div_adr + de1_base);
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break;
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}
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}
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#endif
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for (i = 0; i < len; i++) {
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if (de_clk_tbl[i].clk_no == clk_no) {
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reg_val = readl(de_clk_tbl[i].mod_div_adr + de_base);
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reg_val =
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SET_BITS(de_clk_tbl[i].mod_div_shift,
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de_clk_tbl[i].mod_div_width, reg_val,
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(div - 1));
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writel(reg_val, de_clk_tbl[i].mod_div_adr + de_base);
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return 0;
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}
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}
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__wrn("clk %d not foundis not initializd\n", clk_no);
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return -1;
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}
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static s32 __de_clk_enable(u32 clk_no)
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{
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u32 i;
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u32 reg_val;
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u32 len = sizeof(de_clk_tbl) / sizeof(struct de_clk_para);
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for (i = 0; i < len; i++) {
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if (de_clk_tbl[i].clk_no == clk_no) {
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/* set clk div */
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de_clk_set_div(clk_no, de_clk_tbl[i].div);
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if (de_clk_tbl[i].ahb_reset_shift < 32) {
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reg_val = readl(de_clk_tbl[i].ahb_reset_adr
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+ de_base);
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reg_val =
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SET_BITS(de_clk_tbl[i].ahb_reset_shift, 1,
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reg_val, 1);
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writel(reg_val,
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de_clk_tbl[i].ahb_reset_adr + de_base);
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__inf("clk %d reset enable\n", clk_no);
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}
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if (de_clk_tbl[i].ahb_gate_shift < 32) {
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reg_val =
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readl(de_clk_tbl[i].ahb_gate_adr + de_base);
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reg_val =
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SET_BITS(de_clk_tbl[i].ahb_gate_shift, 1,
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reg_val, 1);
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writel(reg_val,
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de_clk_tbl[i].ahb_gate_adr + de_base);
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__inf("clk %d gate enable\n", clk_no);
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}
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if (de_clk_tbl[i].mod_enable_shift < 32) {
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reg_val =
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readl(de_clk_tbl[i].mod_adr + de_base);
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reg_val =
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SET_BITS(de_clk_tbl[i].mod_enable_shift, 1,
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reg_val, 1);
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writel(reg_val,
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de_clk_tbl[i].mod_adr + de_base);
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__inf("clk %d mod enable\n", clk_no);
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}
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if (de_clk_tbl[i].dram_gate_shift < 32) {
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reg_val =
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readl(de_clk_tbl[i].dram_gate_adr
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+ de_base);
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reg_val =
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SET_BITS(de_clk_tbl[i].dram_gate_shift, 1,
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reg_val, 1);
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writel(reg_val,
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de_clk_tbl[i].dram_gate_adr + de_base);
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__inf("clk %d dram enable\n", clk_no);
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}
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}
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}
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return 0;
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}
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static s32 __de_clk_disable(u32 clk_no)
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{
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u32 i;
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u32 reg_val;
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u32 len = sizeof(de_clk_tbl) / sizeof(struct de_clk_para);
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for (i = 0; i < len; i++) {
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if (de_clk_tbl[i].clk_no != clk_no)
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continue;
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if (de_clk_tbl[i].dram_gate_shift < 32) {
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reg_val =
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readl(de_clk_tbl[i].dram_gate_adr
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+ de_base);
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reg_val =
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SET_BITS(de_clk_tbl[i].dram_gate_shift, 1,
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reg_val, 0);
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writel(reg_val,
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de_clk_tbl[i].dram_gate_adr + de_base);
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__inf("clk %d dram disable\n", clk_no);
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}
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if (de_clk_tbl[i].mod_enable_shift < 32) {
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reg_val =
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readl(de_clk_tbl[i].mod_adr + de_base);
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reg_val =
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SET_BITS(de_clk_tbl[i].mod_enable_shift, 1,
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reg_val, 0);
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writel(reg_val,
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de_clk_tbl[i].mod_adr + de_base);
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__inf("clk %d mod disable\n", clk_no);
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}
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if (de_clk_tbl[i].ahb_gate_shift < 32) {
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reg_val =
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readl(de_clk_tbl[i].ahb_gate_adr + de_base);
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reg_val =
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SET_BITS(de_clk_tbl[i].ahb_gate_shift, 1,
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reg_val, 0);
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writel(reg_val,
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de_clk_tbl[i].ahb_gate_adr + de_base);
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__inf("clk %d gate disable\n", clk_no);
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}
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if (de_clk_tbl[i].ahb_reset_shift < 32) {
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#if defined(DE_WB_RESET_SHARE)
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if ((clk_no == DE_CLK_CORE1)
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|| (clk_no == DE_CLK_WB))
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continue;
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#endif
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reg_val = readl(de_clk_tbl[i].ahb_reset_adr
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+ de_base);
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reg_val = SET_BITS(de_clk_tbl[i].ahb_reset_shift, 1,
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reg_val, 0);
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writel(reg_val, de_clk_tbl[i].ahb_reset_adr + de_base);
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__inf("clk %d reset disable\n", clk_no);
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}
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}
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return 0;
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}
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s32 de_clk_enable(u32 clk_no)
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{
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#if defined(CONFIG_INDEPENDENT_DE)
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void __iomem *tmp = de_base;
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s32 ret = 0;
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if (clk_no == DE_CLK_CORE1) {
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de_base = de1_base;
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ret = __de_clk_enable(DE_CLK_CORE0);
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ret = __de_clk_enable(DE_CLK_WB);
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de_base = tmp;
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} else {
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ret = __de_clk_enable(clk_no);
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}
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return ret;
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#else
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return __de_clk_enable(clk_no);
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#endif
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}
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EXPORT_SYMBOL(de_clk_enable);
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s32 de_clk_disable(u32 clk_no)
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{
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#if defined(CONFIG_INDEPENDENT_DE)
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void __iomem *tmp = de_base;
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s32 ret = 0;
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if (clk_no == DE_CLK_CORE1) {
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de_base = de1_base;
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ret = __de_clk_disable(DE_CLK_CORE0);
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ret = __de_clk_disable(DE_CLK_WB);
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de_base = tmp;
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} else {
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ret = __de_clk_disable(clk_no);
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}
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return ret;
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#else
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return __de_clk_disable(clk_no);
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#endif
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}
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EXPORT_SYMBOL(de_clk_disable);
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s32 de_clk_set_reg_base(uintptr_t reg_base)
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{
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de_base = (void __iomem *)reg_base;
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return 0;
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}
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#if defined(CONFIG_INDEPENDENT_DE)
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s32 de1_clk_set_reg_base(uintptr_t reg_base)
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{
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de1_base = (void __iomem *)reg_base;
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return 0;
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}
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#endif
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