/*
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* Sunxi SD/MMC host driver
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*
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* Copyright (C) 2015 AllWinnertech Ltd.
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* Author: lixiang <lixiang@allwinnertech>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed "as is" WITHOUT ANY WARRANTY of any
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* kind, whether express or implied; without even the implied warranty
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* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/clk.h>
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#include <linux/clk/sunxi.h>
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#include <linux/gpio.h>
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#include <linux/platform_device.h>
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#include <linux/spinlock.h>
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#include <linux/scatterlist.h>
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#include <linux/dma-mapping.h>
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#include <linux/slab.h>
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#include <linux/reset.h>
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#include <linux/of_address.h>
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#include <linux/of_gpio.h>
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#include <linux/of_platform.h>
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#include <linux/mmc/host.h>
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#include <linux/mmc/sd.h>
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#include <linux/mmc/sdio.h>
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#include <linux/mmc/mmc.h>
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#include <linux/mmc/core.h>
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#include <linux/mmc/card.h>
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#include <linux/mmc/slot-gpio.h>
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#ifndef __SUNXI_MMC_H__
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#define __SUNXI_MMC_H__
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#define DRIVER_NAME "sunxi-smhc"
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#define DRIVER_RIVISION "v0.6 2016-4-29 16:53"
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#define DRIVER_VERSION "SD/MMC/SDIO Host Controller Driver(" DRIVER_RIVISION ")"
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#if defined CONFIG_FPGA_V4_PLATFORM || defined CONFIG_FPGA_V7_PLATFORM
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#define MMC_FPGA
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#endif
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#define SMHC_DEVICE_ID (2) /*number of id in multi device*/
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/*max blk count and size is limited by the SMHC_BLK_CFG register's max value*/
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#define MAX_BLK_COUNT (0xFFFF)
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#define MAX_BLK_SIZE (0x800)
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/*#define MAX_DES_SIZE PAGE_SIZE*/
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#define SUNXI_REQ_PAGE_SIZE (PAGE_SIZE*4)
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/*---------------------------------------------*/
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/* registers define */
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/*---------------------------------------------*/
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#define SMHC_CMD_ARG2 (0x00)
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#define SMHC_BLK_CFG (0x04)
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#define SMHC_CMD_ARG1 (0x08)
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#define SMHC_CMD (0x0C)
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#define SMHC_RESP0 (0x10)
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#define SMHC_RESP1 (0x14)
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#define SMHC_RESP2 (0x18)
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#define SMHC_RESP3 (0x1C)
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#define SMHC_BUFF (0x20)
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#define SMHC_STA (0x24)
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#define SMHC_CTRL1 (0x28)
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#define SMHC_RST_CLK_CTRL (0x2C)
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#define SMHC_INT_STA (0x30)
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#define SMHC_INT_STA_EN (0x34)
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#define SMHC_INT_SIG_EN (0x38)
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#define SMHC_ACMD_ERR_CTRL2 (0x3C)
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#define SMHC_SET_ERR (0x50)
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#define SMHC_ADMA_ERR (0x54)
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#define SMHC_ADMA_ADDR (0x58)
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#define SMHC_CTRL3 (0x200)
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#define SMHC_CMD_ATTR (0x204)
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#define SMHC_TO_CTRL2 (0x208)
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#define SMHC_ATC (0x210)
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#define SMHC_RTC (0x214)
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#define SMHC_DITC0 (0x218)
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#define SMHC_DITC1 (0x21C)
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#define SMHC_TP0 (0x220)
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#define SMHC_TP1 (0x224)
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#define SMHC_CRC_STA (0x240)
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#define SMHC_TBC0 (0x244)
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#define SMHC_TBC1 (0x248)
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#define SMHC_BL (0x24C)
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#define SMHC_CEDBN (0x250)
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/*----------------------------------------*/
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#define smhc_readl(host, reg) \
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__raw_readl((host)->reg_base + reg)
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#define smhc_writel(host, reg, value) \
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__raw_writel((value), (host)->reg_base + reg)
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#define smhc_readw(host, reg) \
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__raw_readw((host)->reg_base + reg)
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#define smhc_writew(host, reg, value) \
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__raw_writew((value), (host)->reg_base + reg)
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#define smhc_clr_bit(host, reg, bitmap) \
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do { \
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u32 tmp = smhc_readl(host, reg); \
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tmp &= ~(bitmap); \
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smhc_writel(host, reg, tmp); \
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} while (0)
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#define smhc_set_bit(host, reg, bitmap) \
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do { \
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u32 tmp = smhc_readl(host, reg); \
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tmp |= (bitmap); \
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smhc_writel(host, reg, tmp); \
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} while (0)
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/* control register bit field */
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/*0x2c */
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#define ResetAll (0x1U<<24)
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#define ResetCmd (0x1U<<25)
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#define ResetDat (0x1U<<26)
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#define SdclkEn (0x1U<<2)
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/*0x200 */
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#define CPUAcessBuffEn (0x1U<<31)
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#define StopReadClkAtBlkGap (0x1U<<8)
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#define SWDebounceMode (0x1U<<5)
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#define DebounceEnb (0x1U<<4)
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#define CdDat3En (0x1U<<3)
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#define SdclkIdleCtrl (0x1U<<2)
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/* Struct for SMC Commands */
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/*0x18 */
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#define CMDType (0x3U<<22)
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#define DataExp (0x1U<<21)
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#define CheckRspIdx (0x1U<<20)
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#define CheckRspCRC (0x1U<<19)
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#define NoRsp (0x0U<<16)
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#define Rsp136 (0x1U<<16)
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#define Rsp48 (0x2U<<16)
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#define Rsp48b (0x3U<<16)
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#define SingleBlkTrans (0x0U<<5)
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#define MultiBlkTrans (0x1U<<5)
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#define Read (0x1U<<4)
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#define Write (0x0U<<4)
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#define AutoCmd12 (0x1U<<2)
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#define AutoCmd23 (0x2U<<2)
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#define BlkCntEn (0x1U<<1)
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#define DMAEn (0x1U<<0)
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/*0x204 */
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#define SendInitSeq (0x1U<<4)
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#define DisableBoot (0x1U<<3)
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#define BootACKExp (0x1U<<2)
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#define AltBootMode (0x2U<<0)
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#define MandBootMode (0x1U<<0)
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/*0x03C */
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#define Switch3v3To1v8 (0x1U<<19)
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#define DdrType (0x7<<16)
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#define DDR_SHIFT (16)
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/*0x24 */
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#define CmdLineSta (0x1U<<24)
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#define Dat3LineSta (0x1U<<23)
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#define Dat2LineSta (0x1U<<22)
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#define Dat1LineSta (0x1U<<21)
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#define Dat0LineSta (0x1U<<20)
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#define WpPinSta (0x1U<<19)
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#define CdPinInvSta (0x1U<<18)
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#define CardStable (0x1U<<17)
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#define CardInsert (0x1U<<16)
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#define BuffRDEn (0x1U<<11)
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#define BuffWREn (0x1U<<10)
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#define RDTransActive (0x1U<<9)
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#define WRTransActive (0x1U<<8)
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#define DatLineActive (0x1U<<2)
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#define CmdInhibitDat (0x1U<<1)
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#define CmdInhibitCmd (0x1U<<0)
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#define BootDataStart (0x1U<<29)
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#define BootAckRcv (0x1U<<28)
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#define DSFOInt (0x1U<<30)
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#define DmaErrInt (0x1U<<25)
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#define AcmdErrInt (0x1U<<24)
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#define DatEndBitErrInt (0x1U<<22)
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#define DatCRCErrInt (0x1U<<21)
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#define DatTimeoutErrInt (0x1U<<20)
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#define CmdIdxErrInt (0x1U<<19)
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#define CmdEndBitErrInt (0x1U<<18)
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#define CmdCRCErrInt (0x1U<<17)
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#define CmdTimeoutErrInt (0x1U<<16)
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#define ErrInt (0x1U<<15)
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#define CardInt (0x1U<<8)
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#define CardRemoveInt (0x1U<<7)
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#define CardInsertInt (0x1U<<6)
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#define BuffRDRdyInt (0x1U<<5)
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#define BuffWRRdyInt (0x1U<<4)
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#define DmaInt (0x1U<<3)
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/*#define BlkGapEvtInt (0x1U<<2)*/
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#define TransOverInt (0x1U<<1)
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#define CmdOverInt (0x1U<<0)
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#define TxDatIntBit (DmaInt | TransOverInt | DmaErrInt | ErrInt)
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#define RxDatIntBit (DmaInt | TransOverInt | DmaErrInt | ErrInt)
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#define DmaIntBit (DmaInt | DmaErrInt)
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#define ErrIntBit (0x437F0000) /*(0x1ff<<16)*/
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#define DoneIntBit (TransOverInt|CmdOverInt)
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/*0x28 SMHC_CTRL1 bit field*/
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#define Dma32BitSel (0x3<<3)
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#define DmaSel (0x3<<3)
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#define BusWidth (0x1<<1)
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#define ExtBusWidth (0x1<<5)
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/*0x3C Auto CMD Error Status */
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#define NoAcmd12 (0x1U<<7)
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#define AcmdIdxErr (0x1U<<4)
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#define AcmdEndBitErr (0x1U<<3)
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#define AcmdCRCErr (0x1U<<2)
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#define AcmdTimeoutErr (0x1U<<1)
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#define NotIssueAcmd (0x0<<0)
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enum {
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ACT_NOP = 0,
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ACT_RSV,
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ACT_TRANS,
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ACT_LINK,
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};
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enum {
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MAN_BOOT_MD = 0,
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ALT_BOOT_MD,
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};
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struct sdhc_idma_des {
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/*=1: indicates this line of descriptor is effective.
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*=0: generate ADMA Error interrupt and stop ADMA to prevent runaway.
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*/
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u32 valid:1,
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/*=1: indicates end of descriptor.
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*The Transfer Complete Interrupt is generated
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*when the operation of the descriptor line is completed.
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*/
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end:1,
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/*
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*=1: generates DMA Interrupt
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*when the operation of the descriptor line is completed.
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*/
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int_en:1,
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: 1,
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/*00b: Nop, No Operation, Do not execute current line and go to next line.*/
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act:2,
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/*01b: rsv, reserved, (Same as Nop. Do not execute current line
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*and go to next line.)
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*/
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/*10b: Tran, transfer data, Transfer data of one descriptor
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*line Transfer data of one descriptor line
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*/
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/*11b: Link, Link Descriptor, Link to another descriptor*/
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: 10,
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length:16;
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u32 addr;
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};
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struct sunxi_mmc_ctrl_regs {
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u32 rst_clk_ctrl;
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u32 int_sta_en;
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u32 to;
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u32 ctrl3;
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u32 int_sig_en;
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u32 ctrl1;
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u32 acmd_err_ctrl2;
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u32 atc;
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};
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struct sunxi_mmc_host {
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struct mmc_host *mmc;
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struct reset_control *reset;
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/* IO mapping base */
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void __iomem *reg_base;
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/* clock management */
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struct clk *clk_ahb;
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struct clk *clk_mmc;
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struct clk *clk_rst;
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int (*sunxi_mmc_clk_set_rate)(struct sunxi_mmc_host *host,
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struct mmc_ios *ios);
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/* irq */
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spinlock_t lock;
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int irq;
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u32 int_sum;
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u32 sdio_imask;
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/* dma */
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u32 idma_des_size_bits;
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dma_addr_t sg_dma;
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void *sg_cpu;
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bool wait_dma;
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u32 dma_tl;
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u64 dma_mask;
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void (*sunxi_mmc_thld_ctl)(struct sunxi_mmc_host *host,
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struct mmc_ios *ios,
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struct mmc_data *data);
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struct mmc_request *mrq;
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struct mmc_request *mrq_busy;
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struct mmc_request *manual_stop_mrq;
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int ferror;
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u32 power_on;
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/* pinctrl handles */
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struct pinctrl *pinctrl;
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struct pinctrl_state *pins_default;
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struct pinctrl_state *pins_sleep;
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/*sys node */
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struct device_attribute maual_insert;
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struct device_attribute *dump_register;
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struct device_attribute dump_clk_dly;
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void (*sunxi_mmc_dump_dly_table)(struct sunxi_mmc_host *host);
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/* backup register structrue */
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struct sunxi_mmc_ctrl_regs bak_regs;
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void (*sunxi_mmc_save_spec_reg)(struct sunxi_mmc_host *host);
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void (*sunxi_mmc_restore_spec_reg)(struct sunxi_mmc_host *host);
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void (*sunxi_mmc_set_acmda)(struct sunxi_mmc_host *host);
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void (*sunxi_mmc_shutdown)(struct platform_device *pdev);
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/*really controller id,no logic id */
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int phy_index;
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u32 dat3_imask;
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/*no wait busy if wrtie end, only for customer need */
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#define NO_MANUAL_WAIT_BUSY_WRITE_END 0x1
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#define NO_REINIT_SHUTDOWN 0x2
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#define CARD_PWR_GPIO_HIGH_ACTIVE 0x4
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/*control specal function control,for customer need */
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u32 ctl_spec_cap;
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int card_pwr_gpio;
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void *version_priv_dat;
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};
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/*use to check ddr mode,not include hs400*/
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#define sunxi_mmc_ddr_timing(it) \
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(((it) == MMC_TIMING_UHS_DDR50) || ((it) == MMC_TIMING_MMC_DDR52))
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#endif
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