/*
|
* Atmel ADC driver for SAMA5D2 devices and compatible.
|
*
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* Copyright (C) 2015 Atmel,
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* 2015 Ludovic Desroches <ludovic.desroches@atmel.com>
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
|
|
#include <linux/bitops.h>
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#include <linux/clk.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include <linux/sched.h>
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#include <linux/wait.h>
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#include <linux/iio/iio.h>
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#include <linux/iio/sysfs.h>
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#include <linux/regulator/consumer.h>
|
|
/* Control Register */
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#define AT91_SAMA5D2_CR 0x00
|
/* Software Reset */
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#define AT91_SAMA5D2_CR_SWRST BIT(0)
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/* Start Conversion */
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#define AT91_SAMA5D2_CR_START BIT(1)
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/* Touchscreen Calibration */
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#define AT91_SAMA5D2_CR_TSCALIB BIT(2)
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/* Comparison Restart */
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#define AT91_SAMA5D2_CR_CMPRST BIT(4)
|
|
/* Mode Register */
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#define AT91_SAMA5D2_MR 0x04
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/* Trigger Selection */
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#define AT91_SAMA5D2_MR_TRGSEL(v) ((v) << 1)
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/* ADTRG */
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#define AT91_SAMA5D2_MR_TRGSEL_TRIG0 0
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/* TIOA0 */
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#define AT91_SAMA5D2_MR_TRGSEL_TRIG1 1
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/* TIOA1 */
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#define AT91_SAMA5D2_MR_TRGSEL_TRIG2 2
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/* TIOA2 */
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#define AT91_SAMA5D2_MR_TRGSEL_TRIG3 3
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/* PWM event line 0 */
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#define AT91_SAMA5D2_MR_TRGSEL_TRIG4 4
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/* PWM event line 1 */
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#define AT91_SAMA5D2_MR_TRGSEL_TRIG5 5
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/* TIOA3 */
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#define AT91_SAMA5D2_MR_TRGSEL_TRIG6 6
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/* RTCOUT0 */
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#define AT91_SAMA5D2_MR_TRGSEL_TRIG7 7
|
/* Sleep Mode */
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#define AT91_SAMA5D2_MR_SLEEP BIT(5)
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/* Fast Wake Up */
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#define AT91_SAMA5D2_MR_FWUP BIT(6)
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/* Prescaler Rate Selection */
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#define AT91_SAMA5D2_MR_PRESCAL(v) ((v) << AT91_SAMA5D2_MR_PRESCAL_OFFSET)
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#define AT91_SAMA5D2_MR_PRESCAL_OFFSET 8
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#define AT91_SAMA5D2_MR_PRESCAL_MAX 0xff
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#define AT91_SAMA5D2_MR_PRESCAL_MASK GENMASK(15, 8)
|
/* Startup Time */
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#define AT91_SAMA5D2_MR_STARTUP(v) ((v) << 16)
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#define AT91_SAMA5D2_MR_STARTUP_MASK GENMASK(19, 16)
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/* Analog Change */
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#define AT91_SAMA5D2_MR_ANACH BIT(23)
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/* Tracking Time */
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#define AT91_SAMA5D2_MR_TRACKTIM(v) ((v) << 24)
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#define AT91_SAMA5D2_MR_TRACKTIM_MAX 0xff
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/* Transfer Time */
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#define AT91_SAMA5D2_MR_TRANSFER(v) ((v) << 28)
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#define AT91_SAMA5D2_MR_TRANSFER_MAX 0x3
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/* Use Sequence Enable */
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#define AT91_SAMA5D2_MR_USEQ BIT(31)
|
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/* Channel Sequence Register 1 */
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#define AT91_SAMA5D2_SEQR1 0x08
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/* Channel Sequence Register 2 */
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#define AT91_SAMA5D2_SEQR2 0x0c
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/* Channel Enable Register */
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#define AT91_SAMA5D2_CHER 0x10
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/* Channel Disable Register */
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#define AT91_SAMA5D2_CHDR 0x14
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/* Channel Status Register */
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#define AT91_SAMA5D2_CHSR 0x18
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/* Last Converted Data Register */
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#define AT91_SAMA5D2_LCDR 0x20
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/* Interrupt Enable Register */
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#define AT91_SAMA5D2_IER 0x24
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/* Interrupt Disable Register */
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#define AT91_SAMA5D2_IDR 0x28
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/* Interrupt Mask Register */
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#define AT91_SAMA5D2_IMR 0x2c
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/* Interrupt Status Register */
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#define AT91_SAMA5D2_ISR 0x30
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/* Last Channel Trigger Mode Register */
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#define AT91_SAMA5D2_LCTMR 0x34
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/* Last Channel Compare Window Register */
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#define AT91_SAMA5D2_LCCWR 0x38
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/* Overrun Status Register */
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#define AT91_SAMA5D2_OVER 0x3c
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/* Extended Mode Register */
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#define AT91_SAMA5D2_EMR 0x40
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/* Compare Window Register */
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#define AT91_SAMA5D2_CWR 0x44
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/* Channel Gain Register */
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#define AT91_SAMA5D2_CGR 0x48
|
|
/* Channel Offset Register */
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#define AT91_SAMA5D2_COR 0x4c
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#define AT91_SAMA5D2_COR_DIFF_OFFSET 16
|
|
/* Channel Data Register 0 */
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#define AT91_SAMA5D2_CDR0 0x50
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/* Analog Control Register */
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#define AT91_SAMA5D2_ACR 0x94
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/* Touchscreen Mode Register */
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#define AT91_SAMA5D2_TSMR 0xb0
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/* Touchscreen X Position Register */
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#define AT91_SAMA5D2_XPOSR 0xb4
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/* Touchscreen Y Position Register */
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#define AT91_SAMA5D2_YPOSR 0xb8
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/* Touchscreen Pressure Register */
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#define AT91_SAMA5D2_PRESSR 0xbc
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/* Trigger Register */
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#define AT91_SAMA5D2_TRGR 0xc0
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/* Correction Select Register */
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#define AT91_SAMA5D2_COSR 0xd0
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/* Correction Value Register */
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#define AT91_SAMA5D2_CVR 0xd4
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/* Channel Error Correction Register */
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#define AT91_SAMA5D2_CECR 0xd8
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/* Write Protection Mode Register */
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#define AT91_SAMA5D2_WPMR 0xe4
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/* Write Protection Status Register */
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#define AT91_SAMA5D2_WPSR 0xe8
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/* Version Register */
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#define AT91_SAMA5D2_VERSION 0xfc
|
|
#define AT91_SAMA5D2_CHAN_SINGLE(num, addr) \
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{ \
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.type = IIO_VOLTAGE, \
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.channel = num, \
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.address = addr, \
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.scan_type = { \
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.sign = 'u', \
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.realbits = 12, \
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}, \
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.info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
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.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
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.info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ),\
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.datasheet_name = "CH"#num, \
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.indexed = 1, \
|
}
|
|
#define AT91_SAMA5D2_CHAN_DIFF(num, num2, addr) \
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{ \
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.type = IIO_VOLTAGE, \
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.differential = 1, \
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.channel = num, \
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.channel2 = num2, \
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.address = addr, \
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.scan_type = { \
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.sign = 's', \
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.realbits = 12, \
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}, \
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.info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
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.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
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.info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ),\
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.datasheet_name = "CH"#num"-CH"#num2, \
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.indexed = 1, \
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}
|
|
#define at91_adc_readl(st, reg) readl_relaxed(st->base + reg)
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#define at91_adc_writel(st, reg, val) writel_relaxed(val, st->base + reg)
|
|
struct at91_adc_soc_info {
|
unsigned startup_time;
|
unsigned min_sample_rate;
|
unsigned max_sample_rate;
|
};
|
|
struct at91_adc_state {
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void __iomem *base;
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int irq;
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struct clk *per_clk;
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struct regulator *reg;
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struct regulator *vref;
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int vref_uv;
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const struct iio_chan_spec *chan;
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bool conversion_done;
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u32 conversion_value;
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struct at91_adc_soc_info soc_info;
|
wait_queue_head_t wq_data_available;
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/*
|
* lock to prevent concurrent 'single conversion' requests through
|
* sysfs.
|
*/
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struct mutex lock;
|
};
|
|
static const struct iio_chan_spec at91_adc_channels[] = {
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AT91_SAMA5D2_CHAN_SINGLE(0, 0x50),
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AT91_SAMA5D2_CHAN_SINGLE(1, 0x54),
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AT91_SAMA5D2_CHAN_SINGLE(2, 0x58),
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AT91_SAMA5D2_CHAN_SINGLE(3, 0x5c),
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AT91_SAMA5D2_CHAN_SINGLE(4, 0x60),
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AT91_SAMA5D2_CHAN_SINGLE(5, 0x64),
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AT91_SAMA5D2_CHAN_SINGLE(6, 0x68),
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AT91_SAMA5D2_CHAN_SINGLE(7, 0x6c),
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AT91_SAMA5D2_CHAN_SINGLE(8, 0x70),
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AT91_SAMA5D2_CHAN_SINGLE(9, 0x74),
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AT91_SAMA5D2_CHAN_SINGLE(10, 0x78),
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AT91_SAMA5D2_CHAN_SINGLE(11, 0x7c),
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AT91_SAMA5D2_CHAN_DIFF(0, 1, 0x50),
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AT91_SAMA5D2_CHAN_DIFF(2, 3, 0x58),
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AT91_SAMA5D2_CHAN_DIFF(4, 5, 0x60),
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AT91_SAMA5D2_CHAN_DIFF(6, 7, 0x68),
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AT91_SAMA5D2_CHAN_DIFF(8, 9, 0x70),
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AT91_SAMA5D2_CHAN_DIFF(10, 11, 0x78),
|
};
|
|
static unsigned at91_adc_startup_time(unsigned startup_time_min,
|
unsigned adc_clk_khz)
|
{
|
const unsigned startup_lookup[] = {
|
0, 8, 16, 24,
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64, 80, 96, 112,
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512, 576, 640, 704,
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768, 832, 896, 960
|
};
|
unsigned ticks_min, i;
|
|
/*
|
* Since the adc frequency is checked before, there is no reason
|
* to not meet the startup time constraint.
|
*/
|
|
ticks_min = startup_time_min * adc_clk_khz / 1000;
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for (i = 0; i < ARRAY_SIZE(startup_lookup); i++)
|
if (startup_lookup[i] > ticks_min)
|
break;
|
|
return i;
|
}
|
|
static void at91_adc_setup_samp_freq(struct at91_adc_state *st, unsigned freq)
|
{
|
struct iio_dev *indio_dev = iio_priv_to_dev(st);
|
unsigned f_per, prescal, startup, mr;
|
|
f_per = clk_get_rate(st->per_clk);
|
prescal = (f_per / (2 * freq)) - 1;
|
|
startup = at91_adc_startup_time(st->soc_info.startup_time,
|
freq / 1000);
|
|
mr = at91_adc_readl(st, AT91_SAMA5D2_MR);
|
mr &= ~(AT91_SAMA5D2_MR_STARTUP_MASK | AT91_SAMA5D2_MR_PRESCAL_MASK);
|
mr |= AT91_SAMA5D2_MR_STARTUP(startup);
|
mr |= AT91_SAMA5D2_MR_PRESCAL(prescal);
|
at91_adc_writel(st, AT91_SAMA5D2_MR, mr);
|
|
dev_dbg(&indio_dev->dev, "freq: %u, startup: %u, prescal: %u\n",
|
freq, startup, prescal);
|
}
|
|
static unsigned at91_adc_get_sample_freq(struct at91_adc_state *st)
|
{
|
unsigned f_adc, f_per = clk_get_rate(st->per_clk);
|
unsigned mr, prescal;
|
|
mr = at91_adc_readl(st, AT91_SAMA5D2_MR);
|
prescal = (mr >> AT91_SAMA5D2_MR_PRESCAL_OFFSET)
|
& AT91_SAMA5D2_MR_PRESCAL_MAX;
|
f_adc = f_per / (2 * (prescal + 1));
|
|
return f_adc;
|
}
|
|
static irqreturn_t at91_adc_interrupt(int irq, void *private)
|
{
|
struct iio_dev *indio = private;
|
struct at91_adc_state *st = iio_priv(indio);
|
u32 status = at91_adc_readl(st, AT91_SAMA5D2_ISR);
|
u32 imr = at91_adc_readl(st, AT91_SAMA5D2_IMR);
|
|
if (status & imr) {
|
st->conversion_value = at91_adc_readl(st, st->chan->address);
|
st->conversion_done = true;
|
wake_up_interruptible(&st->wq_data_available);
|
return IRQ_HANDLED;
|
}
|
|
return IRQ_NONE;
|
}
|
|
static int at91_adc_read_raw(struct iio_dev *indio_dev,
|
struct iio_chan_spec const *chan,
|
int *val, int *val2, long mask)
|
{
|
struct at91_adc_state *st = iio_priv(indio_dev);
|
u32 cor = 0;
|
int ret;
|
|
switch (mask) {
|
case IIO_CHAN_INFO_RAW:
|
mutex_lock(&st->lock);
|
|
st->chan = chan;
|
|
if (chan->differential)
|
cor = (BIT(chan->channel) | BIT(chan->channel2)) <<
|
AT91_SAMA5D2_COR_DIFF_OFFSET;
|
|
at91_adc_writel(st, AT91_SAMA5D2_COR, cor);
|
at91_adc_writel(st, AT91_SAMA5D2_CHER, BIT(chan->channel));
|
at91_adc_writel(st, AT91_SAMA5D2_IER, BIT(chan->channel));
|
at91_adc_writel(st, AT91_SAMA5D2_CR, AT91_SAMA5D2_CR_START);
|
|
ret = wait_event_interruptible_timeout(st->wq_data_available,
|
st->conversion_done,
|
msecs_to_jiffies(1000));
|
if (ret == 0)
|
ret = -ETIMEDOUT;
|
|
if (ret > 0) {
|
*val = st->conversion_value;
|
if (chan->scan_type.sign == 's')
|
*val = sign_extend32(*val, 11);
|
ret = IIO_VAL_INT;
|
st->conversion_done = false;
|
}
|
|
at91_adc_writel(st, AT91_SAMA5D2_IDR, BIT(chan->channel));
|
at91_adc_writel(st, AT91_SAMA5D2_CHDR, BIT(chan->channel));
|
|
mutex_unlock(&st->lock);
|
return ret;
|
|
case IIO_CHAN_INFO_SCALE:
|
*val = st->vref_uv / 1000;
|
if (chan->differential)
|
*val *= 2;
|
*val2 = chan->scan_type.realbits;
|
return IIO_VAL_FRACTIONAL_LOG2;
|
|
case IIO_CHAN_INFO_SAMP_FREQ:
|
*val = at91_adc_get_sample_freq(st);
|
return IIO_VAL_INT;
|
|
default:
|
return -EINVAL;
|
}
|
}
|
|
static int at91_adc_write_raw(struct iio_dev *indio_dev,
|
struct iio_chan_spec const *chan,
|
int val, int val2, long mask)
|
{
|
struct at91_adc_state *st = iio_priv(indio_dev);
|
|
if (mask != IIO_CHAN_INFO_SAMP_FREQ)
|
return -EINVAL;
|
|
if (val < st->soc_info.min_sample_rate ||
|
val > st->soc_info.max_sample_rate)
|
return -EINVAL;
|
|
at91_adc_setup_samp_freq(st, val);
|
|
return 0;
|
}
|
|
static const struct iio_info at91_adc_info = {
|
.read_raw = &at91_adc_read_raw,
|
.write_raw = &at91_adc_write_raw,
|
.driver_module = THIS_MODULE,
|
};
|
|
static int at91_adc_probe(struct platform_device *pdev)
|
{
|
struct iio_dev *indio_dev;
|
struct at91_adc_state *st;
|
struct resource *res;
|
int ret;
|
|
indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*st));
|
if (!indio_dev)
|
return -ENOMEM;
|
|
indio_dev->dev.parent = &pdev->dev;
|
indio_dev->name = dev_name(&pdev->dev);
|
indio_dev->modes = INDIO_DIRECT_MODE;
|
indio_dev->info = &at91_adc_info;
|
indio_dev->channels = at91_adc_channels;
|
indio_dev->num_channels = ARRAY_SIZE(at91_adc_channels);
|
|
st = iio_priv(indio_dev);
|
|
ret = of_property_read_u32(pdev->dev.of_node,
|
"atmel,min-sample-rate-hz",
|
&st->soc_info.min_sample_rate);
|
if (ret) {
|
dev_err(&pdev->dev,
|
"invalid or missing value for atmel,min-sample-rate-hz\n");
|
return ret;
|
}
|
|
ret = of_property_read_u32(pdev->dev.of_node,
|
"atmel,max-sample-rate-hz",
|
&st->soc_info.max_sample_rate);
|
if (ret) {
|
dev_err(&pdev->dev,
|
"invalid or missing value for atmel,max-sample-rate-hz\n");
|
return ret;
|
}
|
|
ret = of_property_read_u32(pdev->dev.of_node, "atmel,startup-time-ms",
|
&st->soc_info.startup_time);
|
if (ret) {
|
dev_err(&pdev->dev,
|
"invalid or missing value for atmel,startup-time-ms\n");
|
return ret;
|
}
|
|
init_waitqueue_head(&st->wq_data_available);
|
mutex_init(&st->lock);
|
|
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
if (!res)
|
return -EINVAL;
|
|
st->base = devm_ioremap_resource(&pdev->dev, res);
|
if (IS_ERR(st->base))
|
return PTR_ERR(st->base);
|
|
st->irq = platform_get_irq(pdev, 0);
|
if (st->irq <= 0) {
|
if (!st->irq)
|
st->irq = -ENXIO;
|
|
return st->irq;
|
}
|
|
st->per_clk = devm_clk_get(&pdev->dev, "adc_clk");
|
if (IS_ERR(st->per_clk))
|
return PTR_ERR(st->per_clk);
|
|
st->reg = devm_regulator_get(&pdev->dev, "vddana");
|
if (IS_ERR(st->reg))
|
return PTR_ERR(st->reg);
|
|
st->vref = devm_regulator_get(&pdev->dev, "vref");
|
if (IS_ERR(st->vref))
|
return PTR_ERR(st->vref);
|
|
ret = devm_request_irq(&pdev->dev, st->irq, at91_adc_interrupt, 0,
|
pdev->dev.driver->name, indio_dev);
|
if (ret)
|
return ret;
|
|
ret = regulator_enable(st->reg);
|
if (ret)
|
return ret;
|
|
ret = regulator_enable(st->vref);
|
if (ret)
|
goto reg_disable;
|
|
st->vref_uv = regulator_get_voltage(st->vref);
|
if (st->vref_uv <= 0) {
|
ret = -EINVAL;
|
goto vref_disable;
|
}
|
|
at91_adc_writel(st, AT91_SAMA5D2_CR, AT91_SAMA5D2_CR_SWRST);
|
at91_adc_writel(st, AT91_SAMA5D2_IDR, 0xffffffff);
|
/*
|
* Transfer field must be set to 2 according to the datasheet and
|
* allows different analog settings for each channel.
|
*/
|
at91_adc_writel(st, AT91_SAMA5D2_MR,
|
AT91_SAMA5D2_MR_TRANSFER(2) | AT91_SAMA5D2_MR_ANACH);
|
|
at91_adc_setup_samp_freq(st, st->soc_info.min_sample_rate);
|
|
ret = clk_prepare_enable(st->per_clk);
|
if (ret)
|
goto vref_disable;
|
|
platform_set_drvdata(pdev, indio_dev);
|
|
ret = iio_device_register(indio_dev);
|
if (ret < 0)
|
goto per_clk_disable_unprepare;
|
|
dev_info(&pdev->dev, "version: %x\n",
|
readl_relaxed(st->base + AT91_SAMA5D2_VERSION));
|
|
return 0;
|
|
per_clk_disable_unprepare:
|
clk_disable_unprepare(st->per_clk);
|
vref_disable:
|
regulator_disable(st->vref);
|
reg_disable:
|
regulator_disable(st->reg);
|
return ret;
|
}
|
|
static int at91_adc_remove(struct platform_device *pdev)
|
{
|
struct iio_dev *indio_dev = platform_get_drvdata(pdev);
|
struct at91_adc_state *st = iio_priv(indio_dev);
|
|
iio_device_unregister(indio_dev);
|
|
clk_disable_unprepare(st->per_clk);
|
|
regulator_disable(st->vref);
|
regulator_disable(st->reg);
|
|
return 0;
|
}
|
|
static const struct of_device_id at91_adc_dt_match[] = {
|
{
|
.compatible = "atmel,sama5d2-adc",
|
}, {
|
/* sentinel */
|
}
|
};
|
MODULE_DEVICE_TABLE(of, at91_adc_dt_match);
|
|
static struct platform_driver at91_adc_driver = {
|
.probe = at91_adc_probe,
|
.remove = at91_adc_remove,
|
.driver = {
|
.name = "at91-sama5d2_adc",
|
.of_match_table = at91_adc_dt_match,
|
},
|
};
|
module_platform_driver(at91_adc_driver)
|
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MODULE_AUTHOR("Ludovic Desroches <ludovic.desroches@atmel.com>");
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MODULE_DESCRIPTION("Atmel AT91 SAMA5D2 ADC");
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MODULE_LICENSE("GPL v2");
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