/*
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* r8a7778 processor support
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*
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* Copyright (C) 2013 Renesas Solutions Corp.
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* Copyright (C) 2013 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
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* Copyright (C) 2013 Cogent Embedded, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/clk/renesas.h>
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#include <linux/io.h>
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#include <linux/irqchip.h>
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#include <asm/mach/arch.h>
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#include "common.h"
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#define MODEMR 0xffcc0020
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static void __init r8a7778_timer_init(void)
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{
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u32 mode;
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void __iomem *modemr = ioremap_nocache(MODEMR, 4);
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BUG_ON(!modemr);
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mode = ioread32(modemr);
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iounmap(modemr);
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r8a7778_clocks_init(mode);
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}
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#define INT2SMSKCR0 0x82288 /* 0xfe782288 */
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#define INT2SMSKCR1 0x8228c /* 0xfe78228c */
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#define INT2NTSR0 0x00018 /* 0xfe700018 */
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#define INT2NTSR1 0x0002c /* 0xfe70002c */
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static void __init r8a7778_init_irq_dt(void)
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{
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void __iomem *base = ioremap_nocache(0xfe700000, 0x00100000);
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BUG_ON(!base);
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irqchip_init();
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/* route all interrupts to ARM */
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__raw_writel(0x73ffffff, base + INT2NTSR0);
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__raw_writel(0xffffffff, base + INT2NTSR1);
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/* unmask all known interrupts in INTCS2 */
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__raw_writel(0x08330773, base + INT2SMSKCR0);
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__raw_writel(0x00311110, base + INT2SMSKCR1);
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iounmap(base);
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}
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static const char *const r8a7778_compat_dt[] __initconst = {
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"renesas,r8a7778",
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NULL,
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};
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DT_MACHINE_START(R8A7778_DT, "Generic R8A7778 (Flattened Device Tree)")
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.init_early = shmobile_init_delay,
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.init_irq = r8a7778_init_irq_dt,
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.init_late = shmobile_init_late,
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.init_time = r8a7778_timer_init,
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.dt_compat = r8a7778_compat_dt,
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MACHINE_END
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