// Copyright 2014 the V8 project authors. All rights reserved.
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// Use of this source code is governed by a BSD-style license that can be
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// found in the LICENSE file.
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#include "src/register-configuration.h"
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#include "src/globals.h"
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#include "src/macro-assembler.h"
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namespace v8 {
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namespace internal {
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namespace {
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#define REGISTER_COUNT(R) 1 +
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static const int kMaxAllocatableGeneralRegisterCount =
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ALLOCATABLE_GENERAL_REGISTERS(REGISTER_COUNT)0;
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static const int kMaxAllocatableDoubleRegisterCount =
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ALLOCATABLE_DOUBLE_REGISTERS(REGISTER_COUNT)0;
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static const int kAllocatableGeneralCodes[] = {
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#define REGISTER_CODE(R) kRegCode_##R,
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ALLOCATABLE_GENERAL_REGISTERS(REGISTER_CODE)};
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#undef REGISTER_CODE
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#define REGISTER_CODE(R) kDoubleCode_##R,
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static const int kAllocatableDoubleCodes[] = {
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ALLOCATABLE_DOUBLE_REGISTERS(REGISTER_CODE)};
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#if V8_TARGET_ARCH_ARM
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static const int kAllocatableNoVFP32DoubleCodes[] = {
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ALLOCATABLE_NO_VFP32_DOUBLE_REGISTERS(REGISTER_CODE)};
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#endif // V8_TARGET_ARCH_ARM
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#undef REGISTER_CODE
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static const char* const kGeneralRegisterNames[] = {
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#define REGISTER_NAME(R) #R,
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GENERAL_REGISTERS(REGISTER_NAME)
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#undef REGISTER_NAME
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};
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static const char* const kFloatRegisterNames[] = {
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#define REGISTER_NAME(R) #R,
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FLOAT_REGISTERS(REGISTER_NAME)
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#undef REGISTER_NAME
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};
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static const char* const kDoubleRegisterNames[] = {
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#define REGISTER_NAME(R) #R,
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DOUBLE_REGISTERS(REGISTER_NAME)
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#undef REGISTER_NAME
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};
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static const char* const kSimd128RegisterNames[] = {
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#define REGISTER_NAME(R) #R,
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SIMD128_REGISTERS(REGISTER_NAME)
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#undef REGISTER_NAME
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};
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STATIC_ASSERT(RegisterConfiguration::kMaxGeneralRegisters >=
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Register::kNumRegisters);
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STATIC_ASSERT(RegisterConfiguration::kMaxFPRegisters >=
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FloatRegister::kNumRegisters);
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STATIC_ASSERT(RegisterConfiguration::kMaxFPRegisters >=
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DoubleRegister::kNumRegisters);
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STATIC_ASSERT(RegisterConfiguration::kMaxFPRegisters >=
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Simd128Register::kNumRegisters);
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static int get_num_allocatable_double_registers() {
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return
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#if V8_TARGET_ARCH_IA32
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kMaxAllocatableDoubleRegisterCount;
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#elif V8_TARGET_ARCH_X64
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kMaxAllocatableDoubleRegisterCount;
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#elif V8_TARGET_ARCH_ARM
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CpuFeatures::IsSupported(VFP32DREGS)
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? kMaxAllocatableDoubleRegisterCount
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: (ALLOCATABLE_NO_VFP32_DOUBLE_REGISTERS(REGISTER_COUNT) 0);
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#elif V8_TARGET_ARCH_ARM64
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kMaxAllocatableDoubleRegisterCount;
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#elif V8_TARGET_ARCH_MIPS
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kMaxAllocatableDoubleRegisterCount;
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#elif V8_TARGET_ARCH_MIPS64
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kMaxAllocatableDoubleRegisterCount;
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#elif V8_TARGET_ARCH_PPC
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kMaxAllocatableDoubleRegisterCount;
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#elif V8_TARGET_ARCH_S390
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kMaxAllocatableDoubleRegisterCount;
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#else
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#error Unsupported target architecture.
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#endif
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}
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static const int* get_allocatable_double_codes() {
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return
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#if V8_TARGET_ARCH_ARM
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CpuFeatures::IsSupported(VFP32DREGS) ? kAllocatableDoubleCodes
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: kAllocatableNoVFP32DoubleCodes;
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#else
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kAllocatableDoubleCodes;
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#endif
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}
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class ArchDefaultRegisterConfiguration : public RegisterConfiguration {
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public:
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ArchDefaultRegisterConfiguration()
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: RegisterConfiguration(
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Register::kNumRegisters, DoubleRegister::kNumRegisters,
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kMaxAllocatableGeneralRegisterCount,
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get_num_allocatable_double_registers(), kAllocatableGeneralCodes,
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get_allocatable_double_codes(),
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kSimpleFPAliasing ? AliasingKind::OVERLAP : AliasingKind::COMBINE,
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kGeneralRegisterNames, kFloatRegisterNames, kDoubleRegisterNames,
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kSimd128RegisterNames) {}
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};
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struct RegisterConfigurationInitializer {
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static void Construct(void* config) {
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new (config) ArchDefaultRegisterConfiguration();
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}
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};
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static base::LazyInstance<ArchDefaultRegisterConfiguration,
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RegisterConfigurationInitializer>::type
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kDefaultRegisterConfiguration = LAZY_INSTANCE_INITIALIZER;
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// Allocatable registers with the masking register removed.
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class ArchDefaultPoisoningRegisterConfiguration : public RegisterConfiguration {
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public:
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ArchDefaultPoisoningRegisterConfiguration()
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: RegisterConfiguration(
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Register::kNumRegisters, DoubleRegister::kNumRegisters,
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kMaxAllocatableGeneralRegisterCount - 1,
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get_num_allocatable_double_registers(),
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InitializeGeneralRegisterCodes(), get_allocatable_double_codes(),
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kSimpleFPAliasing ? AliasingKind::OVERLAP : AliasingKind::COMBINE,
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kGeneralRegisterNames, kFloatRegisterNames, kDoubleRegisterNames,
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kSimd128RegisterNames) {}
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private:
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static const int* InitializeGeneralRegisterCodes() {
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int filtered_index = 0;
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for (int i = 0; i < kMaxAllocatableGeneralRegisterCount; ++i) {
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if (kAllocatableGeneralCodes[i] != kSpeculationPoisonRegister.code()) {
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allocatable_general_codes_[filtered_index] =
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kAllocatableGeneralCodes[i];
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filtered_index++;
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}
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}
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DCHECK_EQ(filtered_index, kMaxAllocatableGeneralRegisterCount - 1);
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return allocatable_general_codes_;
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}
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static int
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allocatable_general_codes_[kMaxAllocatableGeneralRegisterCount - 1];
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};
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int ArchDefaultPoisoningRegisterConfiguration::allocatable_general_codes_
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[kMaxAllocatableGeneralRegisterCount - 1];
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struct PoisoningRegisterConfigurationInitializer {
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static void Construct(void* config) {
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new (config) ArchDefaultPoisoningRegisterConfiguration();
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}
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};
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static base::LazyInstance<ArchDefaultPoisoningRegisterConfiguration,
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PoisoningRegisterConfigurationInitializer>::type
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kDefaultPoisoningRegisterConfiguration = LAZY_INSTANCE_INITIALIZER;
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#if defined(V8_TARGET_ARCH_IA32) && defined(V8_EMBEDDED_BUILTINS)
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// Allocatable registers with the root register removed.
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// TODO(v8:6666): Once all builtins have been migrated, we could remove this
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// configuration and remove kRootRegister from ALLOCATABLE_GENERAL_REGISTERS
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// instead.
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class ArchPreserveRootIA32RegisterConfiguration : public RegisterConfiguration {
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public:
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ArchPreserveRootIA32RegisterConfiguration()
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: RegisterConfiguration(
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Register::kNumRegisters, DoubleRegister::kNumRegisters,
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kMaxAllocatableGeneralRegisterCount - 1,
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get_num_allocatable_double_registers(),
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InitializeGeneralRegisterCodes(), get_allocatable_double_codes(),
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kSimpleFPAliasing ? AliasingKind::OVERLAP : AliasingKind::COMBINE,
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kGeneralRegisterNames, kFloatRegisterNames, kDoubleRegisterNames,
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kSimd128RegisterNames) {}
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private:
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static const int* InitializeGeneralRegisterCodes() {
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int filtered_index = 0;
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for (int i = 0; i < kMaxAllocatableGeneralRegisterCount; ++i) {
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if (kAllocatableGeneralCodes[i] != kRootRegister.code()) {
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allocatable_general_codes_[filtered_index] =
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kAllocatableGeneralCodes[i];
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filtered_index++;
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}
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}
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DCHECK_EQ(filtered_index, kMaxAllocatableGeneralRegisterCount - 1);
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return allocatable_general_codes_;
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}
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static int
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allocatable_general_codes_[kMaxAllocatableGeneralRegisterCount - 1];
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};
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int ArchPreserveRootIA32RegisterConfiguration::allocatable_general_codes_
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[kMaxAllocatableGeneralRegisterCount - 1];
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struct PreserveRootIA32RegisterConfigurationInitializer {
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static void Construct(void* config) {
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new (config) ArchPreserveRootIA32RegisterConfiguration();
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}
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};
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static base::LazyInstance<ArchPreserveRootIA32RegisterConfiguration,
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PreserveRootIA32RegisterConfigurationInitializer>::
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type kPreserveRootIA32RegisterConfiguration = LAZY_INSTANCE_INITIALIZER;
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#endif // defined(V8_TARGET_ARCH_IA32) && defined(V8_EMBEDDED_BUILTINS)
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// RestrictedRegisterConfiguration uses the subset of allocatable general
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// registers the architecture support, which results into generating assembly
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// to use less registers. Currently, it's only used by RecordWrite code stub.
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class RestrictedRegisterConfiguration : public RegisterConfiguration {
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public:
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RestrictedRegisterConfiguration(
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int num_allocatable_general_registers,
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std::unique_ptr<int[]> allocatable_general_register_codes,
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std::unique_ptr<char const* []> allocatable_general_register_names)
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: RegisterConfiguration(
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Register::kNumRegisters, DoubleRegister::kNumRegisters,
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num_allocatable_general_registers,
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get_num_allocatable_double_registers(),
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allocatable_general_register_codes.get(),
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get_allocatable_double_codes(),
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kSimpleFPAliasing ? AliasingKind::OVERLAP : AliasingKind::COMBINE,
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kGeneralRegisterNames, kFloatRegisterNames, kDoubleRegisterNames,
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kSimd128RegisterNames),
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allocatable_general_register_codes_(
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std::move(allocatable_general_register_codes)),
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allocatable_general_register_names_(
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std::move(allocatable_general_register_names)) {
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for (int i = 0; i < num_allocatable_general_registers; ++i) {
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DCHECK(
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IsAllocatableGeneralRegister(allocatable_general_register_codes_[i]));
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}
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}
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bool IsAllocatableGeneralRegister(int code) {
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for (int i = 0; i < kMaxAllocatableGeneralRegisterCount; ++i) {
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if (code == kAllocatableGeneralCodes[i]) {
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return true;
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}
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}
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return false;
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}
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private:
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std::unique_ptr<int[]> allocatable_general_register_codes_;
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std::unique_ptr<char const* []> allocatable_general_register_names_;
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};
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} // namespace
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const RegisterConfiguration* RegisterConfiguration::Default() {
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return &kDefaultRegisterConfiguration.Get();
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}
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const RegisterConfiguration* RegisterConfiguration::Poisoning() {
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return &kDefaultPoisoningRegisterConfiguration.Get();
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}
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#if defined(V8_TARGET_ARCH_IA32) && defined(V8_EMBEDDED_BUILTINS)
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const RegisterConfiguration* RegisterConfiguration::PreserveRootIA32() {
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return &kPreserveRootIA32RegisterConfiguration.Get();
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}
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#endif // defined(V8_TARGET_ARCH_IA32) && defined(V8_EMBEDDED_BUILTINS)
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const RegisterConfiguration* RegisterConfiguration::RestrictGeneralRegisters(
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RegList registers) {
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int num = NumRegs(registers);
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std::unique_ptr<int[]> codes{new int[num]};
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std::unique_ptr<char const* []> names { new char const*[num] };
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int counter = 0;
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for (int i = 0; i < Default()->num_allocatable_general_registers(); ++i) {
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auto reg = Register::from_code(Default()->GetAllocatableGeneralCode(i));
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if (reg.bit() & registers) {
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DCHECK(counter < num);
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codes[counter] = reg.code();
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names[counter] = Default()->GetGeneralRegisterName(i);
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counter++;
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}
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}
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return new RestrictedRegisterConfiguration(num, std::move(codes),
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std::move(names));
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}
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RegisterConfiguration::RegisterConfiguration(
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int num_general_registers, int num_double_registers,
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int num_allocatable_general_registers, int num_allocatable_double_registers,
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const int* allocatable_general_codes, const int* allocatable_double_codes,
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AliasingKind fp_aliasing_kind, const char* const* general_register_names,
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const char* const* float_register_names,
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const char* const* double_register_names,
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const char* const* simd128_register_names)
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: num_general_registers_(num_general_registers),
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num_float_registers_(0),
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num_double_registers_(num_double_registers),
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num_simd128_registers_(0),
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num_allocatable_general_registers_(num_allocatable_general_registers),
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num_allocatable_float_registers_(0),
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num_allocatable_double_registers_(num_allocatable_double_registers),
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num_allocatable_simd128_registers_(0),
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allocatable_general_codes_mask_(0),
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allocatable_float_codes_mask_(0),
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allocatable_double_codes_mask_(0),
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allocatable_simd128_codes_mask_(0),
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allocatable_general_codes_(allocatable_general_codes),
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allocatable_double_codes_(allocatable_double_codes),
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fp_aliasing_kind_(fp_aliasing_kind),
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general_register_names_(general_register_names),
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float_register_names_(float_register_names),
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double_register_names_(double_register_names),
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simd128_register_names_(simd128_register_names) {
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DCHECK_LE(num_general_registers_,
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RegisterConfiguration::kMaxGeneralRegisters);
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DCHECK_LE(num_double_registers_, RegisterConfiguration::kMaxFPRegisters);
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for (int i = 0; i < num_allocatable_general_registers_; ++i) {
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allocatable_general_codes_mask_ |= (1 << allocatable_general_codes_[i]);
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}
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for (int i = 0; i < num_allocatable_double_registers_; ++i) {
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allocatable_double_codes_mask_ |= (1 << allocatable_double_codes_[i]);
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}
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if (fp_aliasing_kind_ == COMBINE) {
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num_float_registers_ = num_double_registers_ * 2 <= kMaxFPRegisters
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? num_double_registers_ * 2
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: kMaxFPRegisters;
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num_allocatable_float_registers_ = 0;
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for (int i = 0; i < num_allocatable_double_registers_; i++) {
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int base_code = allocatable_double_codes_[i] * 2;
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if (base_code >= kMaxFPRegisters) continue;
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allocatable_float_codes_[num_allocatable_float_registers_++] = base_code;
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allocatable_float_codes_[num_allocatable_float_registers_++] =
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base_code + 1;
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allocatable_float_codes_mask_ |= (0x3 << base_code);
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}
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num_simd128_registers_ = num_double_registers_ / 2;
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num_allocatable_simd128_registers_ = 0;
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int last_simd128_code = allocatable_double_codes_[0] / 2;
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for (int i = 1; i < num_allocatable_double_registers_; i++) {
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int next_simd128_code = allocatable_double_codes_[i] / 2;
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// This scheme assumes allocatable_double_codes_ are strictly increasing.
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DCHECK_GE(next_simd128_code, last_simd128_code);
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if (last_simd128_code == next_simd128_code) {
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allocatable_simd128_codes_[num_allocatable_simd128_registers_++] =
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next_simd128_code;
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allocatable_simd128_codes_mask_ |= (0x1 << next_simd128_code);
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}
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last_simd128_code = next_simd128_code;
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}
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} else {
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DCHECK(fp_aliasing_kind_ == OVERLAP);
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num_float_registers_ = num_simd128_registers_ = num_double_registers_;
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num_allocatable_float_registers_ = num_allocatable_simd128_registers_ =
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num_allocatable_double_registers_;
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for (int i = 0; i < num_allocatable_float_registers_; ++i) {
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allocatable_float_codes_[i] = allocatable_simd128_codes_[i] =
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allocatable_double_codes_[i];
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}
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allocatable_float_codes_mask_ = allocatable_simd128_codes_mask_ =
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allocatable_double_codes_mask_;
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}
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}
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const char* RegisterConfiguration::GetGeneralOrSpecialRegisterName(
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int code) const {
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if (code < num_general_registers_) return GetGeneralRegisterName(code);
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return Assembler::GetSpecialRegisterName(code);
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}
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// Assert that kFloat32, kFloat64, and kSimd128 are consecutive values.
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STATIC_ASSERT(static_cast<int>(MachineRepresentation::kSimd128) ==
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static_cast<int>(MachineRepresentation::kFloat64) + 1);
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STATIC_ASSERT(static_cast<int>(MachineRepresentation::kFloat64) ==
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static_cast<int>(MachineRepresentation::kFloat32) + 1);
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int RegisterConfiguration::GetAliases(MachineRepresentation rep, int index,
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MachineRepresentation other_rep,
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int* alias_base_index) const {
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DCHECK(fp_aliasing_kind_ == COMBINE);
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DCHECK(IsFloatingPoint(rep) && IsFloatingPoint(other_rep));
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if (rep == other_rep) {
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*alias_base_index = index;
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return 1;
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}
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int rep_int = static_cast<int>(rep);
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int other_rep_int = static_cast<int>(other_rep);
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if (rep_int > other_rep_int) {
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int shift = rep_int - other_rep_int;
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int base_index = index << shift;
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if (base_index >= kMaxFPRegisters) {
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// Alias indices would be out of FP register range.
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return 0;
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}
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*alias_base_index = base_index;
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return 1 << shift;
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}
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int shift = other_rep_int - rep_int;
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*alias_base_index = index >> shift;
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return 1;
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}
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bool RegisterConfiguration::AreAliases(MachineRepresentation rep, int index,
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MachineRepresentation other_rep,
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int other_index) const {
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DCHECK(fp_aliasing_kind_ == COMBINE);
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DCHECK(IsFloatingPoint(rep) && IsFloatingPoint(other_rep));
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if (rep == other_rep) {
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return index == other_index;
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}
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int rep_int = static_cast<int>(rep);
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int other_rep_int = static_cast<int>(other_rep);
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if (rep_int > other_rep_int) {
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int shift = rep_int - other_rep_int;
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return index == other_index >> shift;
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}
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int shift = other_rep_int - rep_int;
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return index >> shift == other_index;
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}
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} // namespace internal
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} // namespace v8
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