//===---------------------- ExecuteStage.cpp --------------------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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/// \file
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///
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/// This file defines the execution stage of an instruction pipeline.
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///
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/// The ExecuteStage is responsible for managing the hardware scheduler
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/// and issuing notifications that an instruction has been executed.
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///
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//===----------------------------------------------------------------------===//
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#include "ExecuteStage.h"
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#include "Scheduler.h"
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/Support/Debug.h"
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#define DEBUG_TYPE "llvm-mca"
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namespace mca {
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using namespace llvm;
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// Reclaim the simulated resources used by the scheduler.
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void ExecuteStage::reclaimSchedulerResources() {
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SmallVector<ResourceRef, 8> ResourcesFreed;
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HWS.reclaimSimulatedResources(ResourcesFreed);
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for (const ResourceRef &RR : ResourcesFreed)
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notifyResourceAvailable(RR);
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}
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// Update the scheduler's instruction queues.
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void ExecuteStage::updateSchedulerQueues() {
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SmallVector<InstRef, 4> InstructionIDs;
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HWS.updateIssuedQueue(InstructionIDs);
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for (const InstRef &IR : InstructionIDs)
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notifyInstructionExecuted(IR);
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InstructionIDs.clear();
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HWS.updatePendingQueue(InstructionIDs);
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for (const InstRef &IR : InstructionIDs)
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notifyInstructionReady(IR);
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}
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// Issue instructions that are waiting in the scheduler's ready queue.
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void ExecuteStage::issueReadyInstructions() {
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SmallVector<InstRef, 4> InstructionIDs;
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InstRef IR = HWS.select();
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while (IR.isValid()) {
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SmallVector<std::pair<ResourceRef, double>, 4> Used;
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HWS.issueInstruction(IR, Used);
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// Reclaim instruction resources and perform notifications.
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const InstrDesc &Desc = IR.getInstruction()->getDesc();
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notifyReleasedBuffers(Desc.Buffers);
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notifyInstructionIssued(IR, Used);
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if (IR.getInstruction()->isExecuted())
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notifyInstructionExecuted(IR);
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// Instructions that have been issued during this cycle might have unblocked
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// other dependent instructions. Dependent instructions may be issued during
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// this same cycle if operands have ReadAdvance entries. Promote those
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// instructions to the ReadyQueue and tell to the caller that we need
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// another round of 'issue()'.
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HWS.promoteToReadyQueue(InstructionIDs);
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for (const InstRef &I : InstructionIDs)
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notifyInstructionReady(I);
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InstructionIDs.clear();
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// Select the next instruction to issue.
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IR = HWS.select();
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}
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}
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// The following routine is the maintenance routine of the ExecuteStage.
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// It is responsible for updating the hardware scheduler (HWS), including
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// reclaiming the HWS's simulated hardware resources, as well as updating the
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// HWS's queues.
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//
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// This routine also processes the instructions that are ready for issuance.
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// These instructions are managed by the HWS's ready queue and can be accessed
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// via the Scheduler::select() routine.
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//
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// Notifications are issued to this stage's listeners when instructions are
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// moved between the HWS's queues. In particular, when an instruction becomes
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// ready or executed.
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void ExecuteStage::cycleStart() {
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reclaimSchedulerResources();
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updateSchedulerQueues();
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issueReadyInstructions();
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}
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// Schedule the instruction for execution on the hardware.
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bool ExecuteStage::execute(InstRef &IR) {
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#ifndef NDEBUG
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// Ensure that the HWS has not stored this instruction in its queues.
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HWS.sanityCheck(IR);
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#endif
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// Reserve a slot in each buffered resource. Also, mark units with
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// BufferSize=0 as reserved. Resources with a buffer size of zero will only
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// be released after MCIS is issued, and all the ResourceCycles for those
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// units have been consumed.
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const InstrDesc &Desc = IR.getInstruction()->getDesc();
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HWS.reserveBuffers(Desc.Buffers);
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notifyReservedBuffers(Desc.Buffers);
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// Obtain a slot in the LSU. If we cannot reserve resources, return true, so
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// that succeeding stages can make progress.
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if (!HWS.reserveResources(IR))
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return true;
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// If we did not return early, then the scheduler is ready for execution.
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notifyInstructionReady(IR);
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// Don't add a zero-latency instruction to the Wait or Ready queue.
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// A zero-latency instruction doesn't consume any scheduler resources. That is
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// because it doesn't need to be executed, and it is often removed at register
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// renaming stage. For example, register-register moves are often optimized at
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// register renaming stage by simply updating register aliases. On some
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// targets, zero-idiom instructions (for example: a xor that clears the value
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// of a register) are treated specially, and are often eliminated at register
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// renaming stage.
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//
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// Instructions that use an in-order dispatch/issue processor resource must be
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// issued immediately to the pipeline(s). Any other in-order buffered
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// resources (i.e. BufferSize=1) is consumed.
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//
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// If we cannot issue immediately, the HWS will add IR to its ready queue for
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// execution later, so we must return early here.
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if (!HWS.issueImmediately(IR))
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return true;
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LLVM_DEBUG(dbgs() << "[SCHEDULER] Instruction #" << IR
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<< " issued immediately\n");
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// Issue IR. The resources for this issuance will be placed in 'Used.'
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SmallVector<std::pair<ResourceRef, double>, 4> Used;
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HWS.issueInstruction(IR, Used);
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// Perform notifications.
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notifyReleasedBuffers(Desc.Buffers);
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notifyInstructionIssued(IR, Used);
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if (IR.getInstruction()->isExecuted())
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notifyInstructionExecuted(IR);
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return true;
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}
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void ExecuteStage::notifyInstructionExecuted(const InstRef &IR) {
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HWS.onInstructionExecuted(IR);
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LLVM_DEBUG(dbgs() << "[E] Instruction Executed: #" << IR << '\n');
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notifyEvent<HWInstructionEvent>(
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HWInstructionEvent(HWInstructionEvent::Executed, IR));
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RCU.onInstructionExecuted(IR.getInstruction()->getRCUTokenID());
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}
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void ExecuteStage::notifyInstructionReady(const InstRef &IR) {
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LLVM_DEBUG(dbgs() << "[E] Instruction Ready: #" << IR << '\n');
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notifyEvent<HWInstructionEvent>(
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HWInstructionEvent(HWInstructionEvent::Ready, IR));
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}
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void ExecuteStage::notifyResourceAvailable(const ResourceRef &RR) {
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LLVM_DEBUG(dbgs() << "[E] Resource Available: [" << RR.first << '.'
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<< RR.second << "]\n");
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for (HWEventListener *Listener : getListeners())
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Listener->onResourceAvailable(RR);
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}
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void ExecuteStage::notifyInstructionIssued(
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const InstRef &IR, ArrayRef<std::pair<ResourceRef, double>> Used) {
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LLVM_DEBUG({
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dbgs() << "[E] Instruction Issued: #" << IR << '\n';
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for (const std::pair<ResourceRef, unsigned> &Resource : Used) {
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dbgs() << "[E] Resource Used: [" << Resource.first.first << '.'
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<< Resource.first.second << "], ";
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dbgs() << "cycles: " << Resource.second << '\n';
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}
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});
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notifyEvent<HWInstructionEvent>(HWInstructionIssuedEvent(IR, Used));
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}
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void ExecuteStage::notifyReservedBuffers(ArrayRef<uint64_t> Buffers) {
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if (Buffers.empty())
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return;
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SmallVector<unsigned, 4> BufferIDs(Buffers.begin(), Buffers.end());
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std::transform(Buffers.begin(), Buffers.end(), BufferIDs.begin(),
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[&](uint64_t Op) { return HWS.getResourceID(Op); });
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for (HWEventListener *Listener : getListeners())
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Listener->onReservedBuffers(BufferIDs);
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}
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void ExecuteStage::notifyReleasedBuffers(ArrayRef<uint64_t> Buffers) {
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if (Buffers.empty())
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return;
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SmallVector<unsigned, 4> BufferIDs(Buffers.begin(), Buffers.end());
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std::transform(Buffers.begin(), Buffers.end(), BufferIDs.begin(),
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[&](uint64_t Op) { return HWS.getResourceID(Op); });
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for (HWEventListener *Listener : getListeners())
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Listener->onReleasedBuffers(BufferIDs);
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}
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} // namespace mca
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