// Copyright 2006 Google Inc. All Rights Reserved.
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// Author: nsanders, menderico
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#ifndef STRESSAPPTEST_OS_H_ // NOLINT
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#define STRESSAPPTEST_OS_H_
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#include <dirent.h>
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#include <unistd.h>
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#include <sys/syscall.h>
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#include <string>
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#include <list>
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#include <map>
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#include <vector>
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// This file must work with autoconf on its public version,
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// so these includes are correct.
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#include "adler32memcpy.h" // NOLINT
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#include "sattypes.h" // NOLINT
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#include "clock.h" // NOLINT
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const char kPagemapPath[] = "/proc/self/pagemap";
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struct PCIDevice {
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int32 domain;
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uint16 bus;
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uint8 dev;
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uint8 func;
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uint16 vendor_id;
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uint16 device_id;
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uint64 base_addr[6];
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uint64 size[6];
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};
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typedef vector<PCIDevice*> PCIDevices;
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class ErrorDiag;
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class Clock;
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// This class implements OS/Platform specific funtions.
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class OsLayer {
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public:
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OsLayer();
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virtual ~OsLayer();
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// Set the minimum amount of hugepages that should be available for testing.
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// Must be set before Initialize().
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void SetMinimumHugepagesSize(int64 min_bytes) {
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min_hugepages_bytes_ = min_bytes;
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}
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// Set the minium amount of memory that should not be allocated. This only
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// has any affect if hugepages are not used.
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// Must be set before Initialize().
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void SetReserveSize(int64 reserve_mb) {
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reserve_mb_ = reserve_mb;
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}
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// Set parameters needed to translate physical address to memory module.
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void SetDramMappingParams(uintptr_t channel_hash, int channel_width,
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vector< vector<string> > *channels) {
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channel_hash_ = channel_hash;
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channel_width_ = channel_width;
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channels_ = channels;
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}
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// Initializes data strctures and open files.
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// Returns false on error.
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virtual bool Initialize();
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// Virtual to physical. This implementation is optional for
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// subclasses to implement.
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// Takes a pointer, and returns the corresponding bus address.
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virtual uint64 VirtualToPhysical(void *vaddr);
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// Prints failed dimm. This implementation is optional for
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// subclasses to implement.
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// Takes a bus address and string, and prints the DIMM name
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// into the string. Returns the DIMM number that corresponds to the
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// address given, or -1 if unable to identify the DIMM number.
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// Note that subclass implementations of FindDimm() MUST fill
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// buf with at LEAST one non-whitespace character (provided len > 0).
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virtual int FindDimm(uint64 addr, char *buf, int len);
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// Classifies addresses according to "regions"
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// This may mean different things on different platforms.
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virtual int32 FindRegion(uint64 paddr);
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// Find cpu cores associated with a region. Either NUMA or arbitrary.
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virtual cpu_set_t *FindCoreMask(int32 region);
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// Return cpu cores associated with a region in a hex string.
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virtual string FindCoreMaskFormat(int32 region);
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// Returns the HD device that contains this file.
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virtual string FindFileDevice(string filename);
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// Returns a list of paths coresponding to HD devices found on this machine.
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virtual list<string> FindFileDevices();
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// Polls for errors. This implementation is optional.
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// This will poll once for errors and return zero iff no errors were found.
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virtual int ErrorPoll();
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// Delay an appropriate amount of time between polling.
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virtual void ErrorWait();
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// Report errors. This implementation is mandatory.
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// This will output a machine readable line regarding the error.
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virtual bool ErrorReport(const char *part, const char *symptom, int count);
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// Flushes page cache. Used to circumvent the page cache when doing disk
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// I/O. This will be a NOP until ActivateFlushPageCache() is called, which
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// is typically done when opening a file with O_DIRECT fails.
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// Returns false on error, true on success or NOP.
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// Subclasses may implement this in machine specific ways..
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virtual bool FlushPageCache(void);
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// Enable FlushPageCache() to actually do the flush instead of being a NOP.
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virtual void ActivateFlushPageCache(void);
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// Flushes cacheline. Used to distinguish read or write errors.
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// Subclasses may implement this in machine specific ways..
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// Takes a pointer, and flushed the cacheline containing that pointer.
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virtual void Flush(void *vaddr);
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// Fast flush, for use in performance critical code.
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// This is bound at compile time, and will not pick up
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// any runtime machine configuration info.
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inline static void FastFlush(void *vaddr) {
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#ifdef STRESSAPPTEST_CPU_PPC
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asm volatile("dcbf 0,%0; sync" : : "r" (vaddr));
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#elif defined(STRESSAPPTEST_CPU_X86_64) || defined(STRESSAPPTEST_CPU_I686)
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// Put mfence before and after clflush to make sure:
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// 1. The write before the clflush is committed to memory bus;
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// 2. The read after the clflush is hitting the memory bus.
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//
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// From Intel manual:
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// CLFLUSH is only ordered by the MFENCE instruction. It is not guaranteed
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// to be ordered by any other fencing, serializing or other CLFLUSH
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// instruction. For example, software can use an MFENCE instruction to
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// insure that previous stores are included in the write-back.
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asm volatile("mfence");
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asm volatile("clflush (%0)" : : "r" (vaddr));
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asm volatile("mfence");
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#elif defined(STRESSAPPTEST_CPU_ARMV7A) && !defined(__aarch64__)
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// ARMv7a cachelines are 8 words (32 bytes).
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syscall(__ARM_NR_cacheflush, vaddr, reinterpret_cast<char*>(vaddr) + 32, 0);
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#else
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#warning "Unsupported CPU type: Unable to force cache flushes."
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#endif
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}
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// Fast flush, for use in performance critical code.
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// This is bound at compile time, and will not pick up
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// any runtime machine configuration info. Takes a NULL-terminated
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// array of addresses to flush.
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inline static void FastFlushList(void **vaddrs) {
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#ifdef STRESSAPPTEST_CPU_PPC
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while (*vaddrs) {
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asm volatile("dcbf 0,%0" : : "r" (*vaddrs++));
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}
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asm volatile("sync");
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#elif defined(STRESSAPPTEST_CPU_X86_64) || defined(STRESSAPPTEST_CPU_I686)
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// Put mfence before and after clflush to make sure:
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// 1. The write before the clflush is committed to memory bus;
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// 2. The read after the clflush is hitting the memory bus.
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//
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// From Intel manual:
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// CLFLUSH is only ordered by the MFENCE instruction. It is not guaranteed
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// to be ordered by any other fencing, serializing or other CLFLUSH
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// instruction. For example, software can use an MFENCE instruction to
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// insure that previous stores are included in the write-back.
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asm volatile("mfence");
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while (*vaddrs) {
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asm volatile("clflush (%0)" : : "r" (*vaddrs++));
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}
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asm volatile("mfence");
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#elif defined(STRESSAPPTEST_CPU_ARMV7A)
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while (*vaddrs) {
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FastFlush(*vaddrs++);
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}
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#else
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#warning "Unsupported CPU type: Unable to force cache flushes."
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#endif
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}
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// Fast flush hint, for use in performance critical code.
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// This is bound at compile time, and will not pick up
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// any runtime machine configuration info. Note that this
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// will not guarantee that a flush happens, but will at least
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// hint that it should. This is useful for speeding up
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// parallel march algorithms.
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inline static void FastFlushHint(void *vaddr) {
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#ifdef STRESSAPPTEST_CPU_PPC
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asm volatile("dcbf 0,%0" : : "r" (vaddr));
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#elif defined(STRESSAPPTEST_CPU_X86_64) || defined(STRESSAPPTEST_CPU_I686)
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// From Intel manual:
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// CLFLUSH is only ordered by the MFENCE instruction. It is not guaranteed
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// to be ordered by any other fencing, serializing or other CLFLUSH
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// instruction. For example, software can use an MFENCE instruction to
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// insure that previous stores are included in the write-back.
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asm volatile("clflush (%0)" : : "r" (vaddr));
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#elif defined(STRESSAPPTEST_CPU_ARMV7A)
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FastFlush(vaddr);
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#else
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#warning "Unsupported CPU type: Unable to force cache flushes."
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#endif
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}
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// Fast flush, for use in performance critical code.
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// This is bound at compile time, and will not pick up
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// any runtime machine configuration info. Sync's any
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// transactions for ordering FastFlushHints.
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inline static void FastFlushSync() {
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#ifdef STRESSAPPTEST_CPU_PPC
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asm volatile("sync");
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#elif defined(STRESSAPPTEST_CPU_X86_64) || defined(STRESSAPPTEST_CPU_I686)
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// Put mfence before and after clflush to make sure:
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// 1. The write before the clflush is committed to memory bus;
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// 2. The read after the clflush is hitting the memory bus.
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//
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// From Intel manual:
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// CLFLUSH is only ordered by the MFENCE instruction. It is not guaranteed
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// to be ordered by any other fencing, serializing or other CLFLUSH
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// instruction. For example, software can use an MFENCE instruction to
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// insure that previous stores are included in the write-back.
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asm volatile("mfence");
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#elif defined(STRESSAPPTEST_CPU_ARMV7A)
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// This is a NOP, FastFlushHint() always does a full flush, so there's
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// nothing to do for FastFlushSync().
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#else
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#warning "Unsupported CPU type: Unable to force cache flushes."
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#endif
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}
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// Get time in cpu timer ticks. Useful for matching MCEs with software
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// actions.
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inline static uint64 GetTimestamp(void) {
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uint64 tsc;
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#ifdef STRESSAPPTEST_CPU_PPC
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uint32 tbl, tbu, temp;
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__asm __volatile(
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"1:\n"
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"mftbu %2\n"
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"mftb %0\n"
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"mftbu %1\n"
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"cmpw %2,%1\n"
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"bne 1b\n"
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: "=r"(tbl), "=r"(tbu), "=r"(temp)
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:
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: "cc");
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tsc = (static_cast<uint64>(tbu) << 32) | static_cast<uint64>(tbl);
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#elif defined(STRESSAPPTEST_CPU_X86_64) || defined(STRESSAPPTEST_CPU_I686)
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datacast_t data;
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__asm __volatile("rdtsc" : "=a" (data.l32.l), "=d"(data.l32.h));
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tsc = data.l64;
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#elif defined(STRESSAPPTEST_CPU_ARMV7A)
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#warning "Unsupported CPU type ARMV7A: your timer may not function correctly"
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tsc = 0;
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#else
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#warning "Unsupported CPU type: your timer may not function correctly"
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tsc = 0;
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#endif
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return (tsc);
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}
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// Find the free memory on the machine.
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virtual int64 FindFreeMemSize();
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// Allocates test memory of length bytes.
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// Subclasses must implement this.
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// Call PepareTestMem to get a pointer.
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virtual int64 AllocateAllMem(); // Returns length.
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// Returns success.
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virtual bool AllocateTestMem(int64 length, uint64 paddr_base);
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virtual void FreeTestMem();
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// Prepares the memory for use. You must call this
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// before using test memory, and after you are done.
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virtual void *PrepareTestMem(uint64 offset, uint64 length);
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virtual void ReleaseTestMem(void *addr, uint64 offset, uint64 length);
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// Machine type detected. Can we implement all these functions correctly?
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// Returns true if machine type is detected and implemented.
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virtual bool IsSupported();
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// Returns 32 for 32-bit, 64 for 64-bit.
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virtual int AddressMode();
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// Update OsLayer state regarding cpu support for various features.
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virtual void GetFeatures();
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// Open, read, write pci cfg through /proc/bus/pci. fd is /proc/pci file.
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virtual int PciOpen(int bus, int device, int function);
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virtual void PciWrite(int fd, uint32 offset, uint32 value, int width);
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virtual uint32 PciRead(int fd, uint32 offset, int width);
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// Read MSRs
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virtual bool ReadMSR(uint32 core, uint32 address, uint64 *data);
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virtual bool WriteMSR(uint32 core, uint32 address, uint64 *data);
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// Extract bits [n+len-1, n] from a 32 bit word.
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// so GetBitField(0x0f00, 8, 4) == 0xf.
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virtual uint32 GetBitField(uint32 val, uint32 n, uint32 len);
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// Platform and CPU specific CPU-stressing function.
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// Returns true on success, false otherwise.
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virtual bool CpuStressWorkload();
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// Causes false errors for unittesting.
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// Setting to "true" causes errors to be injected.
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void set_error_injection(bool errors) { error_injection_ = errors; }
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bool error_injection() const { return error_injection_; }
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// Is SAT using normal malloc'd memory, or exotic mmap'd memory.
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bool normal_mem() const { return normal_mem_; }
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// Get numa config, if available..
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int num_nodes() const { return num_nodes_; }
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int num_cpus() const { return num_cpus_; }
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// Handle to platform-specific error diagnoser.
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ErrorDiag *error_diagnoser_;
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// Disambiguate between different "warm" memcopies.
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virtual bool AdlerMemcpyWarm(uint64 *dstmem, uint64 *srcmem,
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unsigned int size_in_bytes,
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AdlerChecksum *checksum);
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// Store a callback to use to print
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// app-specific info about the last error location.
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// This call back is called with a physical address, and the app can fill in
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// the most recent transaction that occurred at that address.
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typedef bool (*ErrCallback)(uint64 paddr, string *buf);
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void set_err_log_callback(
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ErrCallback err_log_callback) {
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err_log_callback_ = err_log_callback;
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}
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ErrCallback get_err_log_callback() { return err_log_callback_; }
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// Set a clock object that can be overridden for use with unit tests.
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void SetClock(Clock *clock) {
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if (clock_) {
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delete clock_;
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}
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clock_ = clock;
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time_initialized_ = clock_->Now();
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}
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protected:
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void *testmem_; // Location of test memory.
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uint64 testmemsize_; // Size of test memory.
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int64 totalmemsize_; // Size of available memory.
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int64 min_hugepages_bytes_; // Minimum hugepages size.
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int64 reserve_mb_; // Minimum amount of memory to reserve in MB.
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bool error_injection_; // Do error injection?
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bool normal_mem_; // Memory DMA capable?
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bool use_hugepages_; // Use hugepage shmem?
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bool use_posix_shm_; // Use 4k page shmem?
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bool dynamic_mapped_shmem_; // Conserve virtual address space.
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bool mmapped_allocation_; // Was memory allocated using mmap()?
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int shmid_; // Handle to shmem
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vector< vector<string> > *channels_; // Memory module names per channel.
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uint64 channel_hash_; // Mask of address bits XORed for channel.
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int channel_width_; // Channel width in bits.
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int64 regionsize_; // Size of memory "regions"
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int regioncount_; // Number of memory "regions"
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int num_cpus_; // Number of cpus in the system.
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int num_nodes_; // Number of nodes in the system.
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int num_cpus_per_node_; // Number of cpus per node in the system.
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int address_mode_; // Are we running 32 or 64 bit?
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bool has_vector_; // Do we have sse2/neon instructions?
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bool has_clflush_; // Do we have clflush instructions?
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bool use_flush_page_cache_; // Do we need to flush the page cache?
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time_t time_initialized_; // Start time of test.
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vector<cpu_set_t> cpu_sets_; // Cache for cpu masks.
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vector<bool> cpu_sets_valid_; // If the cpu mask cache is valid.
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// Get file descriptor for dev msr.
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virtual int OpenMSR(uint32 core, uint32 address);
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// Look up how many hugepages there are.
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virtual int64 FindHugePages();
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// Link to find last transaction at an error location.
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ErrCallback err_log_callback_;
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// Object to wrap the time function.
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Clock *clock_;
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private:
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DISALLOW_COPY_AND_ASSIGN(OsLayer);
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};
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// Selects and returns the proper OS and hardware interface. Does not call
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// OsLayer::Initialize() on the new object.
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OsLayer *OsLayerFactory(const std::map<std::string, std::string> &options);
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#endif // STRESSAPPTEST_OS_H_ NOLINT
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