/**********************************************************
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* Copyright 2008-2009 VMware, Inc. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person
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* obtaining a copy of this software and associated documentation
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* files (the "Software"), to deal in the Software without
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* restriction, including without limitation the rights to use, copy,
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* modify, merge, publish, distribute, sublicense, and/or sell copies
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* of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*
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**********************************************************/
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#include "pipe/p_defines.h"
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#include "util/u_bitmask.h"
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#include "util/u_format.h"
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#include "util/u_inlines.h"
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#include "util/u_memory.h"
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#include "util/u_math.h"
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#include "util/u_memory.h"
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#include "svga_context.h"
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#include "svga_screen.h"
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#include "svga_state.h"
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#include "svga_cmd.h"
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#include "svga_format.h"
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#include "svga_shader.h"
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struct rs_queue {
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unsigned rs_count;
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SVGA3dRenderState rs[SVGA3D_RS_MAX];
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};
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#define EMIT_RS(svga, value, token) \
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do { \
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STATIC_ASSERT(SVGA3D_RS_##token < ARRAY_SIZE(svga->state.hw_draw.rs)); \
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if (svga->state.hw_draw.rs[SVGA3D_RS_##token] != value) { \
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svga_queue_rs(&queue, SVGA3D_RS_##token, value); \
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svga->state.hw_draw.rs[SVGA3D_RS_##token] = value; \
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} \
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} while (0)
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#define EMIT_RS_FLOAT(svga, fvalue, token) \
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do { \
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unsigned value = fui(fvalue); \
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STATIC_ASSERT(SVGA3D_RS_##token < ARRAY_SIZE(svga->state.hw_draw.rs)); \
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if (svga->state.hw_draw.rs[SVGA3D_RS_##token] != value) { \
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svga_queue_rs(&queue, SVGA3D_RS_##token, value); \
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svga->state.hw_draw.rs[SVGA3D_RS_##token] = value; \
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} \
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} while (0)
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static inline void
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svga_queue_rs(struct rs_queue *q, unsigned rss, unsigned value)
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{
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assert(q->rs_count < ARRAY_SIZE(q->rs));
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q->rs[q->rs_count].state = rss;
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q->rs[q->rs_count].uintValue = value;
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q->rs_count++;
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}
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/* Compare old and new render states and emit differences between them
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* to hardware. Simplest implementation would be to emit the whole of
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* the "to" state.
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*/
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static enum pipe_error
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emit_rss_vgpu9(struct svga_context *svga, unsigned dirty)
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{
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struct svga_screen *screen = svga_screen(svga->pipe.screen);
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struct rs_queue queue;
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float point_size_min;
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queue.rs_count = 0;
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if (dirty & (SVGA_NEW_BLEND | SVGA_NEW_BLEND_COLOR)) {
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const struct svga_blend_state *curr = svga->curr.blend;
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EMIT_RS(svga, curr->rt[0].writemask, COLORWRITEENABLE);
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EMIT_RS(svga, curr->rt[0].blend_enable, BLENDENABLE);
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if (curr->rt[0].blend_enable) {
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EMIT_RS(svga, curr->rt[0].srcblend, SRCBLEND);
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EMIT_RS(svga, curr->rt[0].dstblend, DSTBLEND);
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EMIT_RS(svga, curr->rt[0].blendeq, BLENDEQUATION);
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EMIT_RS(svga, curr->rt[0].separate_alpha_blend_enable,
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SEPARATEALPHABLENDENABLE);
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if (curr->rt[0].separate_alpha_blend_enable) {
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EMIT_RS(svga, curr->rt[0].srcblend_alpha, SRCBLENDALPHA);
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EMIT_RS(svga, curr->rt[0].dstblend_alpha, DSTBLENDALPHA);
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EMIT_RS(svga, curr->rt[0].blendeq_alpha, BLENDEQUATIONALPHA);
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}
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}
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}
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if (dirty & SVGA_NEW_BLEND_COLOR) {
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uint32 color;
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uint32 r = float_to_ubyte(svga->curr.blend_color.color[0]);
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uint32 g = float_to_ubyte(svga->curr.blend_color.color[1]);
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uint32 b = float_to_ubyte(svga->curr.blend_color.color[2]);
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uint32 a = float_to_ubyte(svga->curr.blend_color.color[3]);
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color = (a << 24) | (r << 16) | (g << 8) | b;
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EMIT_RS(svga, color, BLENDCOLOR);
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}
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if (dirty & (SVGA_NEW_DEPTH_STENCIL_ALPHA | SVGA_NEW_RAST)) {
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const struct svga_depth_stencil_state *curr = svga->curr.depth;
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const struct svga_rasterizer_state *rast = svga->curr.rast;
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if (!curr->stencil[0].enabled) {
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/* Stencil disabled
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*/
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EMIT_RS(svga, FALSE, STENCILENABLE);
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EMIT_RS(svga, FALSE, STENCILENABLE2SIDED);
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}
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else if (curr->stencil[0].enabled && !curr->stencil[1].enabled) {
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/* Regular stencil
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*/
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EMIT_RS(svga, TRUE, STENCILENABLE);
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EMIT_RS(svga, FALSE, STENCILENABLE2SIDED);
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EMIT_RS(svga, curr->stencil[0].func, STENCILFUNC);
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EMIT_RS(svga, curr->stencil[0].fail, STENCILFAIL);
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EMIT_RS(svga, curr->stencil[0].zfail, STENCILZFAIL);
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EMIT_RS(svga, curr->stencil[0].pass, STENCILPASS);
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EMIT_RS(svga, curr->stencil_mask, STENCILMASK);
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EMIT_RS(svga, curr->stencil_writemask, STENCILWRITEMASK);
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}
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else {
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int cw, ccw;
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/* Hardware frontwinding is always CW, so if ours is also CW,
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* then our definition of front face agrees with hardware.
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* Otherwise need to flip.
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*/
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if (rast->templ.front_ccw) {
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ccw = 0;
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cw = 1;
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}
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else {
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ccw = 1;
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cw = 0;
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}
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/* Twoside stencil
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*/
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EMIT_RS(svga, TRUE, STENCILENABLE);
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EMIT_RS(svga, TRUE, STENCILENABLE2SIDED);
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EMIT_RS(svga, curr->stencil[cw].func, STENCILFUNC);
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EMIT_RS(svga, curr->stencil[cw].fail, STENCILFAIL);
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EMIT_RS(svga, curr->stencil[cw].zfail, STENCILZFAIL);
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EMIT_RS(svga, curr->stencil[cw].pass, STENCILPASS);
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EMIT_RS(svga, curr->stencil[ccw].func, CCWSTENCILFUNC);
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EMIT_RS(svga, curr->stencil[ccw].fail, CCWSTENCILFAIL);
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EMIT_RS(svga, curr->stencil[ccw].zfail, CCWSTENCILZFAIL);
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EMIT_RS(svga, curr->stencil[ccw].pass, CCWSTENCILPASS);
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EMIT_RS(svga, curr->stencil_mask, STENCILMASK);
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EMIT_RS(svga, curr->stencil_writemask, STENCILWRITEMASK);
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}
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EMIT_RS(svga, curr->zenable, ZENABLE);
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if (curr->zenable) {
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EMIT_RS(svga, curr->zfunc, ZFUNC);
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EMIT_RS(svga, curr->zwriteenable, ZWRITEENABLE);
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}
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EMIT_RS(svga, curr->alphatestenable, ALPHATESTENABLE);
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if (curr->alphatestenable) {
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EMIT_RS(svga, curr->alphafunc, ALPHAFUNC);
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EMIT_RS_FLOAT(svga, curr->alpharef, ALPHAREF);
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}
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}
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if (dirty & SVGA_NEW_STENCIL_REF) {
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EMIT_RS(svga, svga->curr.stencil_ref.ref_value[0], STENCILREF);
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}
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if (dirty & (SVGA_NEW_RAST | SVGA_NEW_NEED_PIPELINE)) {
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const struct svga_rasterizer_state *curr = svga->curr.rast;
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unsigned cullmode = curr->cullmode;
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/* Shademode: still need to rearrange index list to move
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* flat-shading PV first vertex.
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*/
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EMIT_RS(svga, curr->shademode, SHADEMODE);
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/* Don't do culling while the software pipeline is active. It
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* does it for us, and additionally introduces potentially
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* back-facing triangles.
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*/
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if (svga->state.sw.need_pipeline)
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cullmode = SVGA3D_FACE_NONE;
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point_size_min = util_get_min_point_size(&curr->templ);
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EMIT_RS(svga, cullmode, CULLMODE);
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EMIT_RS(svga, curr->scissortestenable, SCISSORTESTENABLE);
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EMIT_RS(svga, curr->multisampleantialias, MULTISAMPLEANTIALIAS);
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EMIT_RS(svga, curr->lastpixel, LASTPIXEL);
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EMIT_RS_FLOAT(svga, curr->pointsize, POINTSIZE);
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EMIT_RS_FLOAT(svga, point_size_min, POINTSIZEMIN);
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EMIT_RS_FLOAT(svga, screen->maxPointSize, POINTSIZEMAX);
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EMIT_RS(svga, curr->pointsprite, POINTSPRITEENABLE);
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/* Emit line state, when the device understands it */
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if (screen->haveLineStipple)
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EMIT_RS(svga, curr->linepattern, LINEPATTERN);
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if (screen->haveLineSmooth)
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EMIT_RS(svga, curr->antialiasedlineenable, ANTIALIASEDLINEENABLE);
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if (screen->maxLineWidth > 1.0F)
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EMIT_RS_FLOAT(svga, curr->linewidth, LINEWIDTH);
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}
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if (dirty & (SVGA_NEW_RAST |
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SVGA_NEW_FRAME_BUFFER |
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SVGA_NEW_NEED_PIPELINE)) {
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const struct svga_rasterizer_state *curr = svga->curr.rast;
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float slope = 0.0;
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float bias = 0.0;
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/* Need to modify depth bias according to bound depthbuffer
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* format. Don't do hardware depthbias while the software
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* pipeline is active.
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*/
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if (!svga->state.sw.need_pipeline &&
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svga->curr.framebuffer.zsbuf)
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{
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slope = curr->slopescaledepthbias;
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bias = svga->curr.depthscale * curr->depthbias;
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}
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EMIT_RS_FLOAT(svga, slope, SLOPESCALEDEPTHBIAS);
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EMIT_RS_FLOAT(svga, bias, DEPTHBIAS);
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}
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if (dirty & SVGA_NEW_FRAME_BUFFER) {
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/* XXX: we only look at the first color buffer's sRGB state */
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float gamma = 1.0f;
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if (svga->curr.framebuffer.cbufs[0] &&
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util_format_is_srgb(svga->curr.framebuffer.cbufs[0]->format)) {
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gamma = 2.2f;
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}
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EMIT_RS_FLOAT(svga, gamma, OUTPUTGAMMA);
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}
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if (dirty & SVGA_NEW_RAST) {
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/* bitmask of the enabled clip planes */
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unsigned enabled = svga->curr.rast->templ.clip_plane_enable;
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EMIT_RS(svga, enabled, CLIPPLANEENABLE);
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}
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if (queue.rs_count) {
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SVGA3dRenderState *rs;
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if (SVGA3D_BeginSetRenderState(svga->swc, &rs, queue.rs_count)
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!= PIPE_OK) {
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/* XXX: need to poison cached hardware state on failure to ensure
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* dirty state gets re-emitted. Fix this by re-instating partial
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* FIFOCommit command and only updating cached hw state once the
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* initial allocation has succeeded.
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*/
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memset(svga->state.hw_draw.rs, 0xcd, sizeof(svga->state.hw_draw.rs));
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return PIPE_ERROR_OUT_OF_MEMORY;
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}
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memcpy(rs, queue.rs, queue.rs_count * sizeof queue.rs[0]);
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SVGA_FIFOCommitAll(svga->swc);
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}
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return PIPE_OK;
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}
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/** Returns a non-culling rasterizer state object to be used with
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* point sprite.
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*/
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static struct svga_rasterizer_state *
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get_no_cull_rasterizer_state(struct svga_context *svga)
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{
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const struct svga_rasterizer_state *r = svga->curr.rast;
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unsigned int aa_point = r->templ.point_smooth;
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if (!svga->rasterizer_no_cull[aa_point]) {
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struct pipe_rasterizer_state rast;
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memset(&rast, 0, sizeof(rast));
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rast.flatshade = 1;
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rast.front_ccw = 1;
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rast.point_smooth = r->templ.point_smooth;
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/* All rasterizer states have the same half_pixel_center,
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* bottom_edge_rule and clip_halfz values since they are
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* constant for a context. If we ever implement
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* GL_ARB_clip_control, the clip_halfz field would have to be observed.
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*/
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rast.half_pixel_center = r->templ.half_pixel_center;
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rast.bottom_edge_rule = r->templ.bottom_edge_rule;
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rast.clip_halfz = r->templ.clip_halfz;
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svga->rasterizer_no_cull[aa_point] =
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svga->pipe.create_rasterizer_state(&svga->pipe, &rast);
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}
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return svga->rasterizer_no_cull[aa_point];
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}
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/** Returns a depth stencil state object with depth and stencil test disabled.
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*/
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static struct svga_depth_stencil_state *
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get_no_depth_stencil_test_state(struct svga_context *svga)
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{
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if (!svga->depthstencil_disable) {
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struct pipe_depth_stencil_alpha_state ds = {{0}};
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svga->depthstencil_disable =
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svga->pipe.create_depth_stencil_alpha_state(&svga->pipe, &ds);
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}
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return svga->depthstencil_disable;
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}
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static enum pipe_error
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emit_rss_vgpu10(struct svga_context *svga, unsigned dirty)
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{
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enum pipe_error ret = PIPE_OK;
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svga_hwtnl_flush_retry(svga);
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if (dirty & (SVGA_NEW_BLEND | SVGA_NEW_BLEND_COLOR)) {
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const struct svga_blend_state *curr;
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float blend_factor[4];
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if (svga_has_any_integer_cbufs(svga)) {
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/* Blending is not supported in integer-valued render targets. */
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curr = svga->noop_blend;
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blend_factor[0] =
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blend_factor[1] =
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blend_factor[2] =
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blend_factor[3] = 0;
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}
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else {
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curr = svga->curr.blend;
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if (curr->blend_color_alpha) {
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blend_factor[0] =
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blend_factor[1] =
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blend_factor[2] =
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blend_factor[3] = svga->curr.blend_color.color[3];
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}
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else {
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blend_factor[0] = svga->curr.blend_color.color[0];
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blend_factor[1] = svga->curr.blend_color.color[1];
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blend_factor[2] = svga->curr.blend_color.color[2];
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blend_factor[3] = svga->curr.blend_color.color[3];
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}
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}
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/* Set/bind the blend state object */
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if (svga->state.hw_draw.blend_id != curr->id ||
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svga->state.hw_draw.blend_factor[0] != blend_factor[0] ||
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svga->state.hw_draw.blend_factor[1] != blend_factor[1] ||
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svga->state.hw_draw.blend_factor[2] != blend_factor[2] ||
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svga->state.hw_draw.blend_factor[3] != blend_factor[3] ||
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svga->state.hw_draw.blend_sample_mask != svga->curr.sample_mask) {
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ret = SVGA3D_vgpu10_SetBlendState(svga->swc, curr->id,
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blend_factor,
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svga->curr.sample_mask);
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if (ret != PIPE_OK)
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return ret;
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svga->state.hw_draw.blend_id = curr->id;
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svga->state.hw_draw.blend_factor[0] = blend_factor[0];
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svga->state.hw_draw.blend_factor[1] = blend_factor[1];
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svga->state.hw_draw.blend_factor[2] = blend_factor[2];
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svga->state.hw_draw.blend_factor[3] = blend_factor[3];
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svga->state.hw_draw.blend_sample_mask = svga->curr.sample_mask;
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}
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}
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if (svga->disable_rasterizer) {
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if (!svga->state.hw_draw.rasterizer_discard) {
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struct svga_depth_stencil_state *ds;
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/* If rasterization is to be disabled, disable depth and stencil
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* testing as well.
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*/
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ds = get_no_depth_stencil_test_state(svga);
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if (ds->id != svga->state.hw_draw.depth_stencil_id) {
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ret = SVGA3D_vgpu10_SetDepthStencilState(svga->swc, ds->id, 0);
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if (ret != PIPE_OK)
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return ret;
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svga->state.hw_draw.depth_stencil_id = ds->id;
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svga->state.hw_draw.stencil_ref = 0;
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}
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svga->state.hw_draw.rasterizer_discard = TRUE;
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}
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} else {
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if ((dirty & (SVGA_NEW_DEPTH_STENCIL_ALPHA | SVGA_NEW_STENCIL_REF)) ||
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svga->state.hw_draw.rasterizer_discard) {
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const struct svga_depth_stencil_state *curr = svga->curr.depth;
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unsigned curr_ref = svga->curr.stencil_ref.ref_value[0];
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if (curr->id != svga->state.hw_draw.depth_stencil_id ||
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curr_ref != svga->state.hw_draw.stencil_ref) {
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/* Set/bind the depth/stencil state object */
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ret = SVGA3D_vgpu10_SetDepthStencilState(svga->swc, curr->id,
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curr_ref);
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if (ret != PIPE_OK)
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return ret;
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svga->state.hw_draw.depth_stencil_id = curr->id;
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svga->state.hw_draw.stencil_ref = curr_ref;
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}
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}
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if (dirty & (SVGA_NEW_REDUCED_PRIMITIVE | SVGA_NEW_RAST)) {
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const struct svga_rasterizer_state *rast;
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if (svga->curr.reduced_prim == PIPE_PRIM_POINTS &&
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svga->curr.gs && svga->curr.gs->wide_point) {
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/* If we are drawing a point sprite, we will need to
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* bind a non-culling rasterizer state object
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*/
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rast = get_no_cull_rasterizer_state(svga);
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}
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else {
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rast = svga->curr.rast;
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}
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if (svga->state.hw_draw.rasterizer_id != rast->id) {
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/* Set/bind the rasterizer state object */
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ret = SVGA3D_vgpu10_SetRasterizerState(svga->swc, rast->id);
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if (ret != PIPE_OK)
|
return ret;
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svga->state.hw_draw.rasterizer_id = rast->id;
|
}
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}
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svga->state.hw_draw.rasterizer_discard = FALSE;
|
}
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return PIPE_OK;
|
}
|
|
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static enum pipe_error
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emit_rss(struct svga_context *svga, unsigned dirty)
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{
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if (svga_have_vgpu10(svga)) {
|
return emit_rss_vgpu10(svga, dirty);
|
}
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else {
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return emit_rss_vgpu9(svga, dirty);
|
}
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}
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|
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struct svga_tracked_state svga_hw_rss =
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{
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"hw rss state",
|
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(SVGA_NEW_BLEND |
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SVGA_NEW_BLEND_COLOR |
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SVGA_NEW_DEPTH_STENCIL_ALPHA |
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SVGA_NEW_STENCIL_REF |
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SVGA_NEW_RAST |
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SVGA_NEW_FRAME_BUFFER |
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SVGA_NEW_NEED_PIPELINE |
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SVGA_NEW_FS |
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SVGA_NEW_REDUCED_PRIMITIVE),
|
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emit_rss
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};
|
