/*
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* Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* on the rights to use, copy, modify, merge, publish, distribute, sub
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* license, and/or sell copies of the Software, and to permit persons to whom
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* the Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
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* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
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* OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
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* USE OR OTHER DEALINGS IN THE SOFTWARE.
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*/
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#include "si_pipe.h"
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#include "radeon/r600_cs.h"
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#include "util/os_time.h"
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void si_destroy_saved_cs(struct si_saved_cs *scs)
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{
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si_clear_saved_cs(&scs->gfx);
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r600_resource_reference(&scs->trace_buf, NULL);
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free(scs);
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}
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/* initialize */
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void si_need_cs_space(struct si_context *ctx)
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{
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struct radeon_winsys_cs *cs = ctx->b.gfx.cs;
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/* There is no need to flush the DMA IB here, because
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* r600_need_dma_space always flushes the GFX IB if there is
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* a conflict, which means any unflushed DMA commands automatically
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* precede the GFX IB (= they had no dependency on the GFX IB when
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* they were submitted).
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*/
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/* There are two memory usage counters in the winsys for all buffers
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* that have been added (cs_add_buffer) and two counters in the pipe
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* driver for those that haven't been added yet.
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*/
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if (unlikely(!radeon_cs_memory_below_limit(ctx->b.screen, ctx->b.gfx.cs,
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ctx->b.vram, ctx->b.gtt))) {
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ctx->b.gtt = 0;
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ctx->b.vram = 0;
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ctx->b.gfx.flush(ctx, PIPE_FLUSH_ASYNC, NULL);
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return;
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}
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ctx->b.gtt = 0;
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ctx->b.vram = 0;
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/* If the CS is sufficiently large, don't count the space needed
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* and just flush if there is not enough space left.
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*/
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if (!ctx->b.ws->cs_check_space(cs, 2048))
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ctx->b.gfx.flush(ctx, PIPE_FLUSH_ASYNC, NULL);
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}
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void si_context_gfx_flush(void *context, unsigned flags,
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struct pipe_fence_handle **fence)
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{
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struct si_context *ctx = context;
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struct radeon_winsys_cs *cs = ctx->b.gfx.cs;
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struct radeon_winsys *ws = ctx->b.ws;
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if (ctx->gfx_flush_in_progress)
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return;
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if (!radeon_emitted(cs, ctx->b.initial_gfx_cs_size))
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return;
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if (si_check_device_reset(&ctx->b))
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return;
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if (ctx->screen->debug_flags & DBG(CHECK_VM))
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flags &= ~PIPE_FLUSH_ASYNC;
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/* If the state tracker is flushing the GFX IB, r600_flush_from_st is
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* responsible for flushing the DMA IB and merging the fences from both.
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* This code is only needed when the driver flushes the GFX IB
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* internally, and it never asks for a fence handle.
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*/
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if (radeon_emitted(ctx->b.dma.cs, 0)) {
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assert(fence == NULL); /* internal flushes only */
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ctx->b.dma.flush(ctx, flags, NULL);
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}
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ctx->gfx_flush_in_progress = true;
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if (!LIST_IS_EMPTY(&ctx->b.active_queries))
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si_suspend_queries(&ctx->b);
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ctx->streamout.suspended = false;
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if (ctx->streamout.begin_emitted) {
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si_emit_streamout_end(ctx);
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ctx->streamout.suspended = true;
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}
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ctx->b.flags |= SI_CONTEXT_CS_PARTIAL_FLUSH |
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SI_CONTEXT_PS_PARTIAL_FLUSH;
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/* DRM 3.1.0 doesn't flush TC for VI correctly. */
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if (ctx->b.chip_class == VI && ctx->b.screen->info.drm_minor <= 1)
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ctx->b.flags |= SI_CONTEXT_INV_GLOBAL_L2 |
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SI_CONTEXT_INV_VMEM_L1;
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si_emit_cache_flush(ctx);
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if (ctx->current_saved_cs) {
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si_trace_emit(ctx);
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si_log_hw_flush(ctx);
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/* Save the IB for debug contexts. */
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si_save_cs(ws, cs, &ctx->current_saved_cs->gfx, true);
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ctx->current_saved_cs->flushed = true;
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ctx->current_saved_cs->time_flush = os_time_get_nano();
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}
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/* Flush the CS. */
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ws->cs_flush(cs, flags, &ctx->b.last_gfx_fence);
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if (fence)
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ws->fence_reference(fence, ctx->b.last_gfx_fence);
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/* This must be after cs_flush returns, since the context's API
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* thread can concurrently read this value in si_fence_finish. */
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ctx->b.num_gfx_cs_flushes++;
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/* Check VM faults if needed. */
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if (ctx->screen->debug_flags & DBG(CHECK_VM)) {
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/* Use conservative timeout 800ms, after which we won't wait any
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* longer and assume the GPU is hung.
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*/
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ctx->b.ws->fence_wait(ctx->b.ws, ctx->b.last_gfx_fence, 800*1000*1000);
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si_check_vm_faults(&ctx->b, &ctx->current_saved_cs->gfx, RING_GFX);
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}
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if (ctx->current_saved_cs)
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si_saved_cs_reference(&ctx->current_saved_cs, NULL);
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si_begin_new_cs(ctx);
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ctx->gfx_flush_in_progress = false;
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}
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static void si_begin_cs_debug(struct si_context *ctx)
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{
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static const uint32_t zeros[1];
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assert(!ctx->current_saved_cs);
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ctx->current_saved_cs = calloc(1, sizeof(*ctx->current_saved_cs));
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if (!ctx->current_saved_cs)
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return;
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pipe_reference_init(&ctx->current_saved_cs->reference, 1);
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ctx->current_saved_cs->trace_buf = (struct r600_resource*)
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pipe_buffer_create(ctx->b.b.screen, 0,
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PIPE_USAGE_STAGING, 8);
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if (!ctx->current_saved_cs->trace_buf) {
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free(ctx->current_saved_cs);
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ctx->current_saved_cs = NULL;
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return;
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}
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pipe_buffer_write_nooverlap(&ctx->b.b, &ctx->current_saved_cs->trace_buf->b.b,
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0, sizeof(zeros), zeros);
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ctx->current_saved_cs->trace_id = 0;
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si_trace_emit(ctx);
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radeon_add_to_buffer_list(&ctx->b, &ctx->b.gfx, ctx->current_saved_cs->trace_buf,
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RADEON_USAGE_READWRITE, RADEON_PRIO_TRACE);
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}
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void si_begin_new_cs(struct si_context *ctx)
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{
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if (ctx->is_debug)
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si_begin_cs_debug(ctx);
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/* Flush read caches at the beginning of CS not flushed by the kernel. */
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if (ctx->b.chip_class >= CIK)
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ctx->b.flags |= SI_CONTEXT_INV_SMEM_L1 |
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SI_CONTEXT_INV_ICACHE;
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ctx->b.flags |= SI_CONTEXT_START_PIPELINE_STATS;
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/* set all valid group as dirty so they get reemited on
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* next draw command
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*/
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si_pm4_reset_emitted(ctx);
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/* The CS initialization should be emitted before everything else. */
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si_pm4_emit(ctx, ctx->init_config);
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if (ctx->init_config_gs_rings)
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si_pm4_emit(ctx, ctx->init_config_gs_rings);
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if (ctx->queued.named.ls)
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ctx->prefetch_L2_mask |= SI_PREFETCH_LS;
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if (ctx->queued.named.hs)
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ctx->prefetch_L2_mask |= SI_PREFETCH_HS;
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if (ctx->queued.named.es)
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ctx->prefetch_L2_mask |= SI_PREFETCH_ES;
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if (ctx->queued.named.gs)
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ctx->prefetch_L2_mask |= SI_PREFETCH_GS;
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if (ctx->queued.named.vs)
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ctx->prefetch_L2_mask |= SI_PREFETCH_VS;
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if (ctx->queued.named.ps)
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ctx->prefetch_L2_mask |= SI_PREFETCH_PS;
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if (ctx->vertex_buffers.buffer && ctx->vertex_elements)
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ctx->prefetch_L2_mask |= SI_PREFETCH_VBO_DESCRIPTORS;
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/* CLEAR_STATE disables all colorbuffers, so only enable bound ones. */
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bool has_clear_state = ctx->screen->has_clear_state;
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if (has_clear_state) {
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ctx->framebuffer.dirty_cbufs =
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u_bit_consecutive(0, ctx->framebuffer.state.nr_cbufs);
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/* CLEAR_STATE disables the zbuffer, so only enable it if it's bound. */
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ctx->framebuffer.dirty_zsbuf = ctx->framebuffer.state.zsbuf != NULL;
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} else {
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ctx->framebuffer.dirty_cbufs = u_bit_consecutive(0, 8);
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ctx->framebuffer.dirty_zsbuf = true;
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}
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/* This should always be marked as dirty to set the framebuffer scissor
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* at least. */
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si_mark_atom_dirty(ctx, &ctx->framebuffer.atom);
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si_mark_atom_dirty(ctx, &ctx->clip_regs);
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/* CLEAR_STATE sets zeros. */
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if (!has_clear_state || ctx->clip_state.any_nonzeros)
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si_mark_atom_dirty(ctx, &ctx->clip_state.atom);
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ctx->msaa_sample_locs.nr_samples = 0;
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si_mark_atom_dirty(ctx, &ctx->msaa_sample_locs.atom);
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si_mark_atom_dirty(ctx, &ctx->msaa_config);
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/* CLEAR_STATE sets 0xffff. */
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if (!has_clear_state || ctx->sample_mask.sample_mask != 0xffff)
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si_mark_atom_dirty(ctx, &ctx->sample_mask.atom);
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si_mark_atom_dirty(ctx, &ctx->cb_render_state);
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/* CLEAR_STATE sets zeros. */
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if (!has_clear_state || ctx->blend_color.any_nonzeros)
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si_mark_atom_dirty(ctx, &ctx->blend_color.atom);
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si_mark_atom_dirty(ctx, &ctx->db_render_state);
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if (ctx->b.chip_class >= GFX9)
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si_mark_atom_dirty(ctx, &ctx->dpbb_state);
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si_mark_atom_dirty(ctx, &ctx->stencil_ref.atom);
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si_mark_atom_dirty(ctx, &ctx->spi_map);
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si_mark_atom_dirty(ctx, &ctx->streamout.enable_atom);
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si_mark_atom_dirty(ctx, &ctx->b.render_cond_atom);
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si_all_descriptors_begin_new_cs(ctx);
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si_all_resident_buffers_begin_new_cs(ctx);
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ctx->scissors.dirty_mask = (1 << SI_MAX_VIEWPORTS) - 1;
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ctx->viewports.dirty_mask = (1 << SI_MAX_VIEWPORTS) - 1;
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ctx->viewports.depth_range_dirty_mask = (1 << SI_MAX_VIEWPORTS) - 1;
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si_mark_atom_dirty(ctx, &ctx->scissors.atom);
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si_mark_atom_dirty(ctx, &ctx->viewports.atom);
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si_mark_atom_dirty(ctx, &ctx->scratch_state);
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if (ctx->scratch_buffer) {
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si_context_add_resource_size(&ctx->b.b,
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&ctx->scratch_buffer->b.b);
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}
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if (ctx->streamout.suspended) {
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ctx->streamout.append_bitmask = ctx->streamout.enabled_mask;
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si_streamout_buffers_dirty(ctx);
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}
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if (!LIST_IS_EMPTY(&ctx->b.active_queries))
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si_resume_queries(&ctx->b);
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assert(!ctx->b.gfx.cs->prev_dw);
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ctx->b.initial_gfx_cs_size = ctx->b.gfx.cs->current.cdw;
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/* Invalidate various draw states so that they are emitted before
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* the first draw call. */
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si_invalidate_draw_sh_constants(ctx);
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ctx->last_index_size = -1;
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ctx->last_primitive_restart_en = -1;
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ctx->last_restart_index = SI_RESTART_INDEX_UNKNOWN;
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ctx->last_gs_out_prim = -1;
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ctx->last_prim = -1;
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ctx->last_multi_vgt_param = -1;
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ctx->last_rast_prim = -1;
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ctx->last_sc_line_stipple = ~0;
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ctx->last_vs_state = ~0;
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ctx->last_ls = NULL;
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ctx->last_tcs = NULL;
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ctx->last_tes_sh_base = -1;
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ctx->last_num_tcs_input_cp = -1;
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ctx->cs_shader_state.initialized = false;
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}
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