/*
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* Copyright 2013 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* on the rights to use, copy, modify, merge, publish, distribute, sub
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* license, and/or sell copies of the Software, and to permit persons to whom
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* the Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
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* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
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* OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
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* USE OR OTHER DEALINGS IN THE SOFTWARE.
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*/
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#include "si_pipe.h"
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#include "sid.h"
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#include "radeon/r600_cs.h"
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/* Recommended maximum sizes for optimal performance.
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* Fall back to compute or SDMA if the size is greater.
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*/
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#define CP_DMA_COPY_PERF_THRESHOLD (64 * 1024) /* copied from Vulkan */
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#define CP_DMA_CLEAR_PERF_THRESHOLD (32 * 1024) /* guess (clear is much slower) */
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/* Set this if you want the ME to wait until CP DMA is done.
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* It should be set on the last CP DMA packet. */
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#define CP_DMA_SYNC (1 << 0)
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/* Set this if the source data was used as a destination in a previous CP DMA
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* packet. It's for preventing a read-after-write (RAW) hazard between two
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* CP DMA packets. */
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#define CP_DMA_RAW_WAIT (1 << 1)
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#define CP_DMA_USE_L2 (1 << 2) /* CIK+ */
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#define CP_DMA_CLEAR (1 << 3)
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/* The max number of bytes that can be copied per packet. */
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static inline unsigned cp_dma_max_byte_count(struct si_context *sctx)
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{
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unsigned max = sctx->b.chip_class >= GFX9 ?
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S_414_BYTE_COUNT_GFX9(~0u) :
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S_414_BYTE_COUNT_GFX6(~0u);
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/* make it aligned for optimal performance */
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return max & ~(SI_CPDMA_ALIGNMENT - 1);
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}
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/* Emit a CP DMA packet to do a copy from one buffer to another, or to clear
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* a buffer. The size must fit in bits [20:0]. If CP_DMA_CLEAR is set, src_va is a 32-bit
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* clear value.
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*/
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static void si_emit_cp_dma(struct si_context *sctx, uint64_t dst_va,
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uint64_t src_va, unsigned size, unsigned flags,
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enum r600_coherency coher)
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{
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struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
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uint32_t header = 0, command = 0;
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assert(size);
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assert(size <= cp_dma_max_byte_count(sctx));
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if (sctx->b.chip_class >= GFX9)
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command |= S_414_BYTE_COUNT_GFX9(size);
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else
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command |= S_414_BYTE_COUNT_GFX6(size);
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/* Sync flags. */
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if (flags & CP_DMA_SYNC)
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header |= S_411_CP_SYNC(1);
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else {
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if (sctx->b.chip_class >= GFX9)
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command |= S_414_DISABLE_WR_CONFIRM_GFX9(1);
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else
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command |= S_414_DISABLE_WR_CONFIRM_GFX6(1);
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}
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if (flags & CP_DMA_RAW_WAIT)
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command |= S_414_RAW_WAIT(1);
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/* Src and dst flags. */
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if (sctx->b.chip_class >= GFX9 && !(flags & CP_DMA_CLEAR) &&
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src_va == dst_va)
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header |= S_411_DSL_SEL(V_411_NOWHERE); /* prefetch only */
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else if (flags & CP_DMA_USE_L2)
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header |= S_411_DSL_SEL(V_411_DST_ADDR_TC_L2);
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if (flags & CP_DMA_CLEAR)
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header |= S_411_SRC_SEL(V_411_DATA);
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else if (flags & CP_DMA_USE_L2)
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header |= S_411_SRC_SEL(V_411_SRC_ADDR_TC_L2);
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if (sctx->b.chip_class >= CIK) {
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radeon_emit(cs, PKT3(PKT3_DMA_DATA, 5, 0));
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radeon_emit(cs, header);
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radeon_emit(cs, src_va); /* SRC_ADDR_LO [31:0] */
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radeon_emit(cs, src_va >> 32); /* SRC_ADDR_HI [31:0] */
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radeon_emit(cs, dst_va); /* DST_ADDR_LO [31:0] */
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radeon_emit(cs, dst_va >> 32); /* DST_ADDR_HI [31:0] */
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radeon_emit(cs, command);
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} else {
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header |= S_411_SRC_ADDR_HI(src_va >> 32);
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radeon_emit(cs, PKT3(PKT3_CP_DMA, 4, 0));
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radeon_emit(cs, src_va); /* SRC_ADDR_LO [31:0] */
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radeon_emit(cs, header); /* SRC_ADDR_HI [15:0] + flags. */
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radeon_emit(cs, dst_va); /* DST_ADDR_LO [31:0] */
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radeon_emit(cs, (dst_va >> 32) & 0xffff); /* DST_ADDR_HI [15:0] */
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radeon_emit(cs, command);
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}
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/* CP DMA is executed in ME, but index buffers are read by PFP.
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* This ensures that ME (CP DMA) is idle before PFP starts fetching
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* indices. If we wanted to execute CP DMA in PFP, this packet
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* should precede it.
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*/
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if (coher == R600_COHERENCY_SHADER && flags & CP_DMA_SYNC) {
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radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
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radeon_emit(cs, 0);
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}
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}
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static unsigned get_flush_flags(struct si_context *sctx, enum r600_coherency coher)
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{
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switch (coher) {
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default:
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case R600_COHERENCY_NONE:
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return 0;
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case R600_COHERENCY_SHADER:
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return SI_CONTEXT_INV_SMEM_L1 |
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SI_CONTEXT_INV_VMEM_L1 |
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(sctx->b.chip_class == SI ? SI_CONTEXT_INV_GLOBAL_L2 : 0);
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case R600_COHERENCY_CB_META:
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return SI_CONTEXT_FLUSH_AND_INV_CB;
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}
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}
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static unsigned get_tc_l2_flag(struct si_context *sctx, enum r600_coherency coher)
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{
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if ((sctx->b.chip_class >= GFX9 && coher == R600_COHERENCY_CB_META) ||
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(sctx->b.chip_class >= CIK && coher == R600_COHERENCY_SHADER))
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return CP_DMA_USE_L2;
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return 0;
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}
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static void si_cp_dma_prepare(struct si_context *sctx, struct pipe_resource *dst,
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struct pipe_resource *src, unsigned byte_count,
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uint64_t remaining_size, unsigned user_flags,
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bool *is_first, unsigned *packet_flags)
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{
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/* Fast exit for a CPDMA prefetch. */
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if ((user_flags & SI_CPDMA_SKIP_ALL) == SI_CPDMA_SKIP_ALL) {
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*is_first = false;
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return;
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}
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if (!(user_flags & SI_CPDMA_SKIP_BO_LIST_UPDATE)) {
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/* Count memory usage in so that need_cs_space can take it into account. */
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si_context_add_resource_size(&sctx->b.b, dst);
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if (src)
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si_context_add_resource_size(&sctx->b.b, src);
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}
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if (!(user_flags & SI_CPDMA_SKIP_CHECK_CS_SPACE))
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si_need_cs_space(sctx);
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/* This must be done after need_cs_space. */
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if (!(user_flags & SI_CPDMA_SKIP_BO_LIST_UPDATE)) {
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radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
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(struct r600_resource*)dst,
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RADEON_USAGE_WRITE, RADEON_PRIO_CP_DMA);
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if (src)
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radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
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(struct r600_resource*)src,
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RADEON_USAGE_READ, RADEON_PRIO_CP_DMA);
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}
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/* Flush the caches for the first copy only.
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* Also wait for the previous CP DMA operations.
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*/
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if (!(user_flags & SI_CPDMA_SKIP_GFX_SYNC) && sctx->b.flags)
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si_emit_cache_flush(sctx);
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if (!(user_flags & SI_CPDMA_SKIP_SYNC_BEFORE) && *is_first)
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*packet_flags |= CP_DMA_RAW_WAIT;
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*is_first = false;
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/* Do the synchronization after the last dma, so that all data
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* is written to memory.
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*/
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if (!(user_flags & SI_CPDMA_SKIP_SYNC_AFTER) &&
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byte_count == remaining_size)
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*packet_flags |= CP_DMA_SYNC;
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}
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void si_clear_buffer(struct pipe_context *ctx, struct pipe_resource *dst,
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uint64_t offset, uint64_t size, unsigned value,
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enum r600_coherency coher)
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{
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struct si_context *sctx = (struct si_context*)ctx;
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struct radeon_winsys *ws = sctx->b.ws;
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struct r600_resource *rdst = r600_resource(dst);
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unsigned tc_l2_flag = get_tc_l2_flag(sctx, coher);
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unsigned flush_flags = get_flush_flags(sctx, coher);
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uint64_t dma_clear_size;
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bool is_first = true;
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if (!size)
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return;
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dma_clear_size = size & ~3ull;
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/* Mark the buffer range of destination as valid (initialized),
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* so that transfer_map knows it should wait for the GPU when mapping
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* that range. */
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util_range_add(&rdst->valid_buffer_range, offset,
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offset + dma_clear_size);
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/* dma_clear_buffer can use clear_buffer on failure. Make sure that
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* doesn't happen. We don't want an infinite recursion: */
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if (sctx->b.dma.cs &&
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!(dst->flags & PIPE_RESOURCE_FLAG_SPARSE) &&
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(offset % 4 == 0) &&
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/* CP DMA is very slow. Always use SDMA for big clears. This
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* alone improves DeusEx:MD performance by 70%. */
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(size > CP_DMA_CLEAR_PERF_THRESHOLD ||
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/* Buffers not used by the GFX IB yet will be cleared by SDMA.
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* This happens to move most buffer clears to SDMA, including
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* DCC and CMASK clears, because pipe->clear clears them before
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* si_emit_framebuffer_state (in a draw call) adds them.
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* For example, DeusEx:MD has 21 buffer clears per frame and all
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* of them are moved to SDMA thanks to this. */
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!ws->cs_is_buffer_referenced(sctx->b.gfx.cs, rdst->buf,
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RADEON_USAGE_READWRITE))) {
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sctx->b.dma_clear_buffer(ctx, dst, offset, dma_clear_size, value);
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offset += dma_clear_size;
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size -= dma_clear_size;
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} else if (dma_clear_size >= 4) {
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uint64_t va = rdst->gpu_address + offset;
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offset += dma_clear_size;
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size -= dma_clear_size;
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/* Flush the caches. */
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sctx->b.flags |= SI_CONTEXT_PS_PARTIAL_FLUSH |
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SI_CONTEXT_CS_PARTIAL_FLUSH | flush_flags;
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while (dma_clear_size) {
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unsigned byte_count = MIN2(dma_clear_size, cp_dma_max_byte_count(sctx));
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unsigned dma_flags = tc_l2_flag | CP_DMA_CLEAR;
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si_cp_dma_prepare(sctx, dst, NULL, byte_count, dma_clear_size, 0,
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&is_first, &dma_flags);
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/* Emit the clear packet. */
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si_emit_cp_dma(sctx, va, value, byte_count, dma_flags, coher);
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dma_clear_size -= byte_count;
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va += byte_count;
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}
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if (tc_l2_flag)
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rdst->TC_L2_dirty = true;
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/* If it's not a framebuffer fast clear... */
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if (coher == R600_COHERENCY_SHADER)
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sctx->b.num_cp_dma_calls++;
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}
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if (size) {
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/* Handle non-dword alignment.
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*
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* This function is called for embedded texture metadata clears,
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* but those should always be properly aligned. */
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assert(dst->target == PIPE_BUFFER);
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assert(size < 4);
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pipe_buffer_write(ctx, dst, offset, size, &value);
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}
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}
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static void si_pipe_clear_buffer(struct pipe_context *ctx,
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struct pipe_resource *dst,
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unsigned offset, unsigned size,
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const void *clear_value_ptr,
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int clear_value_size)
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{
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struct si_context *sctx = (struct si_context*)ctx;
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uint32_t dword_value;
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unsigned i;
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assert(offset % clear_value_size == 0);
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assert(size % clear_value_size == 0);
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if (clear_value_size > 4) {
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const uint32_t *u32 = clear_value_ptr;
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bool clear_dword_duplicated = true;
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/* See if we can lower large fills to dword fills. */
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for (i = 1; i < clear_value_size / 4; i++)
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if (u32[0] != u32[i]) {
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clear_dword_duplicated = false;
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break;
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}
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if (!clear_dword_duplicated) {
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/* Use transform feedback for 64-bit, 96-bit, and
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* 128-bit fills.
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*/
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union pipe_color_union clear_value;
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memcpy(&clear_value, clear_value_ptr, clear_value_size);
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si_blitter_begin(ctx, SI_DISABLE_RENDER_COND);
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util_blitter_clear_buffer(sctx->blitter, dst, offset,
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size, clear_value_size / 4,
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&clear_value);
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si_blitter_end(ctx);
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return;
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}
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}
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/* Expand the clear value to a dword. */
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switch (clear_value_size) {
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case 1:
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dword_value = *(uint8_t*)clear_value_ptr;
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dword_value |= (dword_value << 8) |
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(dword_value << 16) |
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(dword_value << 24);
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break;
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case 2:
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dword_value = *(uint16_t*)clear_value_ptr;
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dword_value |= dword_value << 16;
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break;
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default:
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dword_value = *(uint32_t*)clear_value_ptr;
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}
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si_clear_buffer(ctx, dst, offset, size, dword_value,
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R600_COHERENCY_SHADER);
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}
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/**
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* Realign the CP DMA engine. This must be done after a copy with an unaligned
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* size.
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*
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* \param size Remaining size to the CP DMA alignment.
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*/
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static void si_cp_dma_realign_engine(struct si_context *sctx, unsigned size,
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unsigned user_flags, bool *is_first)
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{
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uint64_t va;
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unsigned dma_flags = 0;
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unsigned scratch_size = SI_CPDMA_ALIGNMENT * 2;
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assert(size < SI_CPDMA_ALIGNMENT);
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/* Use the scratch buffer as the dummy buffer. The 3D engine should be
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* idle at this point.
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*/
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if (!sctx->scratch_buffer ||
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sctx->scratch_buffer->b.b.width0 < scratch_size) {
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r600_resource_reference(&sctx->scratch_buffer, NULL);
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sctx->scratch_buffer = (struct r600_resource*)
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si_aligned_buffer_create(&sctx->screen->b,
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R600_RESOURCE_FLAG_UNMAPPABLE,
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PIPE_USAGE_DEFAULT,
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scratch_size, 256);
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if (!sctx->scratch_buffer)
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return;
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si_mark_atom_dirty(sctx, &sctx->scratch_state);
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}
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si_cp_dma_prepare(sctx, &sctx->scratch_buffer->b.b,
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&sctx->scratch_buffer->b.b, size, size, user_flags,
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is_first, &dma_flags);
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va = sctx->scratch_buffer->gpu_address;
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si_emit_cp_dma(sctx, va, va + SI_CPDMA_ALIGNMENT, size, dma_flags,
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R600_COHERENCY_SHADER);
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}
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/**
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* Do memcpy between buffers using CP DMA.
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*
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* \param user_flags bitmask of SI_CPDMA_*
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*/
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void si_copy_buffer(struct si_context *sctx,
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struct pipe_resource *dst, struct pipe_resource *src,
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uint64_t dst_offset, uint64_t src_offset, unsigned size,
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unsigned user_flags)
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{
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uint64_t main_dst_offset, main_src_offset;
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unsigned skipped_size = 0;
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unsigned realign_size = 0;
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unsigned tc_l2_flag = get_tc_l2_flag(sctx, R600_COHERENCY_SHADER);
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unsigned flush_flags = get_flush_flags(sctx, R600_COHERENCY_SHADER);
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bool is_first = true;
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if (!size)
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return;
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if (dst != src || dst_offset != src_offset) {
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/* Mark the buffer range of destination as valid (initialized),
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* so that transfer_map knows it should wait for the GPU when mapping
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* that range. */
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util_range_add(&r600_resource(dst)->valid_buffer_range, dst_offset,
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dst_offset + size);
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}
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dst_offset += r600_resource(dst)->gpu_address;
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src_offset += r600_resource(src)->gpu_address;
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/* The workarounds aren't needed on Fiji and beyond. */
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if (sctx->b.family <= CHIP_CARRIZO ||
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sctx->b.family == CHIP_STONEY) {
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/* If the size is not aligned, we must add a dummy copy at the end
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* just to align the internal counter. Otherwise, the DMA engine
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* would slow down by an order of magnitude for following copies.
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*/
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if (size % SI_CPDMA_ALIGNMENT)
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realign_size = SI_CPDMA_ALIGNMENT - (size % SI_CPDMA_ALIGNMENT);
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/* If the copy begins unaligned, we must start copying from the next
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* aligned block and the skipped part should be copied after everything
|
* else has been copied. Only the src alignment matters, not dst.
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*/
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if (src_offset % SI_CPDMA_ALIGNMENT) {
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skipped_size = SI_CPDMA_ALIGNMENT - (src_offset % SI_CPDMA_ALIGNMENT);
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/* The main part will be skipped if the size is too small. */
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skipped_size = MIN2(skipped_size, size);
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size -= skipped_size;
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}
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}
|
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/* Flush the caches. */
|
if (!(user_flags & SI_CPDMA_SKIP_GFX_SYNC))
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sctx->b.flags |= SI_CONTEXT_PS_PARTIAL_FLUSH |
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SI_CONTEXT_CS_PARTIAL_FLUSH | flush_flags;
|
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/* This is the main part doing the copying. Src is always aligned. */
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main_dst_offset = dst_offset + skipped_size;
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main_src_offset = src_offset + skipped_size;
|
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while (size) {
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unsigned dma_flags = tc_l2_flag;
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unsigned byte_count = MIN2(size, cp_dma_max_byte_count(sctx));
|
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si_cp_dma_prepare(sctx, dst, src, byte_count,
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size + skipped_size + realign_size,
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user_flags, &is_first, &dma_flags);
|
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si_emit_cp_dma(sctx, main_dst_offset, main_src_offset,
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byte_count, dma_flags, R600_COHERENCY_SHADER);
|
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size -= byte_count;
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main_src_offset += byte_count;
|
main_dst_offset += byte_count;
|
}
|
|
/* Copy the part we skipped because src wasn't aligned. */
|
if (skipped_size) {
|
unsigned dma_flags = tc_l2_flag;
|
|
si_cp_dma_prepare(sctx, dst, src, skipped_size,
|
skipped_size + realign_size, user_flags,
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&is_first, &dma_flags);
|
|
si_emit_cp_dma(sctx, dst_offset, src_offset, skipped_size,
|
dma_flags, R600_COHERENCY_SHADER);
|
}
|
|
/* Finally, realign the engine if the size wasn't aligned. */
|
if (realign_size)
|
si_cp_dma_realign_engine(sctx, realign_size, user_flags,
|
&is_first);
|
|
if (tc_l2_flag)
|
r600_resource(dst)->TC_L2_dirty = true;
|
|
/* If it's not a prefetch... */
|
if (dst_offset != src_offset)
|
sctx->b.num_cp_dma_calls++;
|
}
|
|
void cik_prefetch_TC_L2_async(struct si_context *sctx, struct pipe_resource *buf,
|
uint64_t offset, unsigned size)
|
{
|
assert(sctx->b.chip_class >= CIK);
|
|
si_copy_buffer(sctx, buf, buf, offset, offset, size, SI_CPDMA_SKIP_ALL);
|
}
|
|
static void cik_prefetch_shader_async(struct si_context *sctx,
|
struct si_pm4_state *state)
|
{
|
struct pipe_resource *bo = &state->bo[0]->b.b;
|
assert(state->nbo == 1);
|
|
cik_prefetch_TC_L2_async(sctx, bo, 0, bo->width0);
|
}
|
|
static void cik_prefetch_VBO_descriptors(struct si_context *sctx)
|
{
|
if (!sctx->vertex_elements)
|
return;
|
|
cik_prefetch_TC_L2_async(sctx, &sctx->vertex_buffers.buffer->b.b,
|
sctx->vertex_buffers.gpu_address -
|
sctx->vertex_buffers.buffer->gpu_address,
|
sctx->vertex_elements->desc_list_byte_size);
|
}
|
|
void cik_emit_prefetch_L2(struct si_context *sctx)
|
{
|
/* Prefetch shaders and VBO descriptors to TC L2. */
|
if (sctx->b.chip_class >= GFX9) {
|
/* Choose the right spot for the VBO prefetch. */
|
if (sctx->tes_shader.cso) {
|
if (sctx->prefetch_L2_mask & SI_PREFETCH_HS)
|
cik_prefetch_shader_async(sctx, sctx->queued.named.hs);
|
if (sctx->prefetch_L2_mask & SI_PREFETCH_VBO_DESCRIPTORS)
|
cik_prefetch_VBO_descriptors(sctx);
|
if (sctx->prefetch_L2_mask & SI_PREFETCH_GS)
|
cik_prefetch_shader_async(sctx, sctx->queued.named.gs);
|
if (sctx->prefetch_L2_mask & SI_PREFETCH_VS)
|
cik_prefetch_shader_async(sctx, sctx->queued.named.vs);
|
} else if (sctx->gs_shader.cso) {
|
if (sctx->prefetch_L2_mask & SI_PREFETCH_GS)
|
cik_prefetch_shader_async(sctx, sctx->queued.named.gs);
|
if (sctx->prefetch_L2_mask & SI_PREFETCH_VBO_DESCRIPTORS)
|
cik_prefetch_VBO_descriptors(sctx);
|
if (sctx->prefetch_L2_mask & SI_PREFETCH_VS)
|
cik_prefetch_shader_async(sctx, sctx->queued.named.vs);
|
} else {
|
if (sctx->prefetch_L2_mask & SI_PREFETCH_VS)
|
cik_prefetch_shader_async(sctx, sctx->queued.named.vs);
|
if (sctx->prefetch_L2_mask & SI_PREFETCH_VBO_DESCRIPTORS)
|
cik_prefetch_VBO_descriptors(sctx);
|
}
|
} else {
|
/* SI-CI-VI */
|
/* Choose the right spot for the VBO prefetch. */
|
if (sctx->tes_shader.cso) {
|
if (sctx->prefetch_L2_mask & SI_PREFETCH_LS)
|
cik_prefetch_shader_async(sctx, sctx->queued.named.ls);
|
if (sctx->prefetch_L2_mask & SI_PREFETCH_VBO_DESCRIPTORS)
|
cik_prefetch_VBO_descriptors(sctx);
|
if (sctx->prefetch_L2_mask & SI_PREFETCH_HS)
|
cik_prefetch_shader_async(sctx, sctx->queued.named.hs);
|
if (sctx->prefetch_L2_mask & SI_PREFETCH_ES)
|
cik_prefetch_shader_async(sctx, sctx->queued.named.es);
|
if (sctx->prefetch_L2_mask & SI_PREFETCH_GS)
|
cik_prefetch_shader_async(sctx, sctx->queued.named.gs);
|
if (sctx->prefetch_L2_mask & SI_PREFETCH_VS)
|
cik_prefetch_shader_async(sctx, sctx->queued.named.vs);
|
} else if (sctx->gs_shader.cso) {
|
if (sctx->prefetch_L2_mask & SI_PREFETCH_ES)
|
cik_prefetch_shader_async(sctx, sctx->queued.named.es);
|
if (sctx->prefetch_L2_mask & SI_PREFETCH_VBO_DESCRIPTORS)
|
cik_prefetch_VBO_descriptors(sctx);
|
if (sctx->prefetch_L2_mask & SI_PREFETCH_GS)
|
cik_prefetch_shader_async(sctx, sctx->queued.named.gs);
|
if (sctx->prefetch_L2_mask & SI_PREFETCH_VS)
|
cik_prefetch_shader_async(sctx, sctx->queued.named.vs);
|
} else {
|
if (sctx->prefetch_L2_mask & SI_PREFETCH_VS)
|
cik_prefetch_shader_async(sctx, sctx->queued.named.vs);
|
if (sctx->prefetch_L2_mask & SI_PREFETCH_VBO_DESCRIPTORS)
|
cik_prefetch_VBO_descriptors(sctx);
|
}
|
}
|
|
if (sctx->prefetch_L2_mask & SI_PREFETCH_PS)
|
cik_prefetch_shader_async(sctx, sctx->queued.named.ps);
|
|
sctx->prefetch_L2_mask = 0;
|
}
|
|
void si_init_cp_dma_functions(struct si_context *sctx)
|
{
|
sctx->b.b.clear_buffer = si_pipe_clear_buffer;
|
}
|
