/**************************************************************************
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*
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* Copyright 2017 Advanced Micro Devices, Inc.
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* All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the
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* "Software"), to deal in the Software without restriction, including
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* without limitation the rights to use, copy, modify, merge, publish,
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* distribute, sub license, and/or sell copies of the Software, and to
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* permit persons to whom the Software is furnished to do so, subject to
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* the following conditions:
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*
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* The above copyright notice and this permission notice (including the
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* next paragraph) shall be included in all copies or substantial portions
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* of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
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* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
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* IN NO EVENT SHALL THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR
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* ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
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* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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**************************************************************************/
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#ifndef _RADEON_VCN_ENC_H
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#define _RADEON_VCN_ENC_H
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#define RENCODE_FW_INTERFACE_MAJOR_VERSION 1
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#define RENCODE_FW_INTERFACE_MINOR_VERSION 2
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#define RENCODE_IB_PARAM_SESSION_INFO 0x00000001
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#define RENCODE_IB_PARAM_TASK_INFO 0x00000002
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#define RENCODE_IB_PARAM_SESSION_INIT 0x00000003
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#define RENCODE_IB_PARAM_LAYER_CONTROL 0x00000004
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#define RENCODE_IB_PARAM_LAYER_SELECT 0x00000005
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#define RENCODE_IB_PARAM_RATE_CONTROL_SESSION_INIT 0x00000006
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#define RENCODE_IB_PARAM_RATE_CONTROL_LAYER_INIT 0x00000007
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#define RENCODE_IB_PARAM_RATE_CONTROL_PER_PICTURE 0x00000008
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#define RENCODE_IB_PARAM_QUALITY_PARAMS 0x00000009
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#define RENCODE_IB_PARAM_SLICE_HEADER 0x0000000a
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#define RENCODE_IB_PARAM_ENCODE_PARAMS 0x0000000b
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#define RENCODE_IB_PARAM_INTRA_REFRESH 0x0000000c
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#define RENCODE_IB_PARAM_ENCODE_CONTEXT_BUFFER 0x0000000d
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#define RENCODE_IB_PARAM_VIDEO_BITSTREAM_BUFFER 0x0000000e
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#define RENCODE_IB_PARAM_FEEDBACK_BUFFER 0x00000010
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#define RENCODE_IB_PARAM_DIRECT_OUTPUT_NALU 0x00000020
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#define RENCODE_H264_IB_PARAM_SLICE_CONTROL 0x00200001
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#define RENCODE_H264_IB_PARAM_SPEC_MISC 0x00200002
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#define RENCODE_H264_IB_PARAM_ENCODE_PARAMS 0x00200003
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#define RENCODE_H264_IB_PARAM_DEBLOCKING_FILTER 0x00200004
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#define RENCODE_IB_OP_INITIALIZE 0x01000001
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#define RENCODE_IB_OP_CLOSE_SESSION 0x01000002
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#define RENCODE_IB_OP_ENCODE 0x01000003
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#define RENCODE_IB_OP_INIT_RC 0x01000004
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#define RENCODE_IB_OP_INIT_RC_VBV_BUFFER_LEVEL 0x01000005
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#define RENCODE_IB_OP_SET_SPEED_ENCODING_MODE 0x01000006
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#define RENCODE_IB_OP_SET_BALANCE_ENCODING_MODE 0x01000007
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#define RENCODE_IB_OP_SET_QUALITY_ENCODING_MODE 0x01000008
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#define RENCODE_IF_MAJOR_VERSION_MASK 0xFFFF0000
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#define RENCODE_IF_MAJOR_VERSION_SHIFT 16
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#define RENCODE_IF_MINOR_VERSION_MASK 0x0000FFFF
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#define RENCODE_IF_MINOR_VERSION_SHIFT 0
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#define RENCODE_ENCODE_STANDARD_H264 1
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#define RENCODE_PREENCODE_MODE_NONE 0x00000000
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#define RENCODE_PREENCODE_MODE_1X 0x00000001
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#define RENCODE_PREENCODE_MODE_2X 0x00000002
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#define RENCODE_PREENCODE_MODE_4X 0x00000004
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#define RENCODE_H264_SLICE_CONTROL_MODE_FIXED_MBS 0x00000000
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#define RENCODE_H264_SLICE_CONTROL_MODE_FIXED_BITS 0x00000001
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#define RENCODE_RATE_CONTROL_METHOD_NONE 0x00000000
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#define RENCODE_RATE_CONTROL_METHOD_LATENCY_CONSTRAINED_VBR 0x00000001
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#define RENCODE_RATE_CONTROL_METHOD_PEAK_CONSTRAINED_VBR 0x00000002
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#define RENCODE_RATE_CONTROL_METHOD_CBR 0x00000003
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#define RENCODE_DIRECT_OUTPUT_NALU_TYPE_AUD 0x00000000
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#define RENCODE_DIRECT_OUTPUT_NALU_TYPE_VPS 0x00000001
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#define RENCODE_DIRECT_OUTPUT_NALU_TYPE_SPS 0x00000002
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#define RENCODE_DIRECT_OUTPUT_NALU_TYPE_PPS 0x00000003
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#define RENCODE_DIRECT_OUTPUT_NALU_TYPE_PREFIX 0x00000004
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#define RENCODE_DIRECT_OUTPUT_NALU_TYPE_END_OF_SEQUENCE 0x00000005
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#define RENCODE_SLICE_HEADER_TEMPLATE_MAX_TEMPLATE_SIZE_IN_DWORDS 16
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#define RENCODE_SLICE_HEADER_TEMPLATE_MAX_NUM_INSTRUCTIONS 16
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#define RENCODE_HEADER_INSTRUCTION_END 0x00000000
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#define RENCODE_HEADER_INSTRUCTION_COPY 0x00000001
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#define RENCODE_H264_HEADER_INSTRUCTION_FIRST_MB 0x00020000
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#define RENCODE_H264_HEADER_INSTRUCTION_SLICE_QP_DELTA 0x00020001
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#define RENCODE_PICTURE_TYPE_B 0
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#define RENCODE_PICTURE_TYPE_P 1
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#define RENCODE_PICTURE_TYPE_I 2
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#define RENCODE_PICTURE_TYPE_P_SKIP 3
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#define RENCODE_INPUT_SWIZZLE_MODE_LINEAR 0
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#define RENCODE_INPUT_SWIZZLE_MODE_256B_S 1
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#define RENCODE_INPUT_SWIZZLE_MODE_4kB_S 5
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#define RENCODE_INPUT_SWIZZLE_MODE_64kB_S 9
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#define RENCODE_H264_PICTURE_STRUCTURE_FRAME 0
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#define RENCODE_H264_PICTURE_STRUCTURE_TOP_FIELD 1
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#define RENCODE_H264_PICTURE_STRUCTURE_BOTTOM_FIELD 2
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#define RENCODE_H264_INTERLACING_MODE_PROGRESSIVE 0
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#define RENCODE_H264_INTERLACING_MODE_INTERLACED_STACKED 1
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#define RENCODE_H264_INTERLACING_MODE_INTERLACED_INTERLEAVED 2
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#define RENCODE_H264_DISABLE_DEBLOCKING_FILTER_IDC_ENABLE 0
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#define RENCODE_H264_DISABLE_DEBLOCKING_FILTER_IDC_DISABLE 1
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#define RENCODE_H264_DISABLE_DEBLOCKING_FILTER_IDC_DISALBE_ACROSS_SLICE_BOUNDARY 2
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#define RENCODE_INTRA_REFRESH_MODE_NONE 0
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#define RENCODE_INTRA_REFRESH_MODE_CTB_MB_ROWS 1
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#define RENCODE_INTRA_REFRESH_MODE_CTB_MB_COLUMNS 2
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#define RENCODE_MAX_NUM_RECONSTRUCTED_PICTURES 34
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#define RENCODE_REC_SWIZZLE_MODE_LINEAR 0
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#define RENCODE_REC_SWIZZLE_MODE_256B_S 1
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#define RENCODE_VIDEO_BITSTREAM_BUFFER_MODE_LINEAR 0
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#define RENCODE_VIDEO_BITSTREAM_BUFFER_MODE_CIRCULAR 1
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#define RENCODE_FEEDBACK_BUFFER_MODE_LINEAR 0
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#define RENCODE_FEEDBACK_BUFFER_MODE_CIRCULAR 1
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typedef struct rvcn_enc_session_info_s
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{
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uint32_t interface_version;
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uint32_t sw_context_address_hi;
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uint32_t sw_context_address_lo;
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} rvcn_enc_session_info_t;
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typedef struct rvcn_enc_task_info_s
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{
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uint32_t total_size_of_all_packages;
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uint32_t task_id;
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uint32_t allowed_max_num_feedbacks;
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} rvcn_enc_task_info_t;
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typedef struct rvcn_enc_session_init_s
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{
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uint32_t encode_standard;
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uint32_t aligned_picture_width;
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uint32_t aligned_picture_height;
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uint32_t padding_width;
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uint32_t padding_height;
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uint32_t pre_encode_mode;
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uint32_t pre_encode_chroma_enabled;
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} rvcn_enc_session_init_t;
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typedef struct rvcn_enc_layer_control_s
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{
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uint32_t max_num_temporal_layers;
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uint32_t num_temporal_layers;
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} rvcn_enc_layer_control_t;
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typedef struct rvcn_enc_layer_select_s
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{
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uint32_t temporal_layer_index;
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} rvcn_enc_layer_select_t;
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typedef struct rvcn_enc_h264_slice_control_s
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{
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uint32_t slice_control_mode;
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union
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{
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uint32_t num_mbs_per_slice;
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uint32_t num_bits_per_slice;
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};
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} rvcn_enc_h264_slice_control_t;
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typedef struct rvcn_enc_h264_spec_misc_s
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{
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uint32_t constrained_intra_pred_flag;
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uint32_t cabac_enable;
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uint32_t cabac_init_idc;
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uint32_t half_pel_enabled;
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uint32_t quarter_pel_enabled;
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uint32_t profile_idc;
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uint32_t level_idc;
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} rvcn_enc_h264_spec_misc_t;
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typedef struct rvcn_enc_rate_ctl_session_init_s
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{
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uint32_t rate_control_method;
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uint32_t vbv_buffer_level;
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} rvcn_enc_rate_ctl_session_init_t;
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typedef struct rvcn_enc_rate_ctl_layer_init_s
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{
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uint32_t target_bit_rate;
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uint32_t peak_bit_rate;
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uint32_t frame_rate_num;
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uint32_t frame_rate_den;
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uint32_t vbv_buffer_size;
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uint32_t avg_target_bits_per_picture;
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uint32_t peak_bits_per_picture_integer;
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uint32_t peak_bits_per_picture_fractional;
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} rvcn_enc_rate_ctl_layer_init_t;
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typedef struct rvcn_enc_rate_ctl_per_picture_s
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{
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uint32_t qp;
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uint32_t min_qp_app;
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uint32_t max_qp_app;
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uint32_t max_au_size;
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uint32_t enabled_filler_data;
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uint32_t skip_frame_enable;
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uint32_t enforce_hrd;
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} rvcn_enc_rate_ctl_per_picture_t;
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typedef struct rvcn_enc_quality_params_s
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{
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uint32_t vbaq_mode;
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uint32_t scene_change_sensitivity;
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uint32_t scene_change_min_idr_interval;
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} rvcn_enc_quality_params_t;
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typedef struct rvcn_enc_direct_output_nalu_s
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{
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uint32_t type;
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uint32_t size;
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uint32_t data[1];
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} rvcn_enc_direct_output_nalu_t;
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typedef struct rvcn_enc_slice_header_s
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{
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uint32_t bitstream_template[RENCODE_SLICE_HEADER_TEMPLATE_MAX_TEMPLATE_SIZE_IN_DWORDS];
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struct {
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uint32_t instruction;
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uint32_t num_bits;
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} instructions[RENCODE_SLICE_HEADER_TEMPLATE_MAX_NUM_INSTRUCTIONS];
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} rvcn_enc_slice_header_t;
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typedef struct rvcn_enc_encode_params_s
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{
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uint32_t pic_type;
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uint32_t allowed_max_bitstream_size;
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uint32_t input_picture_luma_address_hi;
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uint32_t input_picture_luma_address_lo;
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uint32_t input_picture_chroma_address_hi;
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uint32_t input_picture_chroma_address_lo;
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uint32_t input_pic_luma_pitch;
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uint32_t input_pic_chroma_pitch;
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uint8_t input_pic_swizzle_mode;
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uint32_t reference_picture_index;
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uint32_t reconstructed_picture_index;
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} rvcn_enc_encode_params_t;
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typedef struct rvcn_enc_h264_encode_params_s
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{
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uint32_t input_picture_structure;
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uint32_t interlaced_mode;
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uint32_t reference_picture_structure;
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uint32_t reference_picture1_index;
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} rvcn_enc_h264_encode_params_t;
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typedef struct rvcn_enc_h264_deblocking_filter_s
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{
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uint32_t disable_deblocking_filter_idc;
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int32_t alpha_c0_offset_div2;
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int32_t beta_offset_div2;
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int32_t cb_qp_offset;
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int32_t cr_qp_offset;
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} rvcn_enc_h264_deblocking_filter_t;
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typedef struct rvcn_enc_intra_refresh_s
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{
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uint32_t intra_refresh_mode;
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uint32_t offset;
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uint32_t region_size;
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} rvcn_enc_intra_refresh_t;
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typedef struct rvcn_enc_reconstructed_picture_s
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{
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uint32_t luma_offset;
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uint32_t chroma_offset;
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} rvcn_enc_reconstructed_picture_t;
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typedef struct rvcn_enc_encode_context_buffer_s
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{
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uint32_t encode_context_address_hi;
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uint32_t encode_context_address_lo;
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uint32_t swizzle_mode;
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uint32_t rec_luma_pitch;
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uint32_t rec_chroma_pitch;
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uint32_t num_reconstructed_pictures;
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rvcn_enc_reconstructed_picture_t reconstructed_pictures[RENCODE_MAX_NUM_RECONSTRUCTED_PICTURES];
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uint32_t pre_encode_picture_luma_pitch;
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uint32_t pre_encode_picture_chroma_pitch;
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rvcn_enc_reconstructed_picture_t pre_encode_reconstructed_pictures[RENCODE_MAX_NUM_RECONSTRUCTED_PICTURES];
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rvcn_enc_reconstructed_picture_t pre_encode_input_picture;
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} rvcn_enc_encode_context_buffer_t;
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typedef struct rvcn_enc_video_bitstream_buffer_s
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{
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uint32_t mode;
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uint32_t video_bitstream_buffer_address_hi;
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uint32_t video_bitstream_buffer_address_lo;
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uint32_t video_bitstream_buffer_size;
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uint32_t video_bitstream_data_offset;
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} rvcn_enc_video_bitstream_buffer_t;
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typedef struct rvcn_enc_feedback_buffer_s
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{
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uint32_t mode;
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uint32_t feedback_buffer_address_hi;
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uint32_t feedback_buffer_address_lo;
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uint32_t feedback_buffer_size;
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uint32_t feedback_data_size;
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} rvcn_enc_feedback_buffer_t;
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typedef void (*radeon_enc_get_buffer)(struct pipe_resource *resource,
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struct pb_buffer **handle,
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struct radeon_surf **surface);
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struct pipe_video_codec *radeon_create_encoder(struct pipe_context *context,
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const struct pipe_video_codec *templat,
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struct radeon_winsys* ws,
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radeon_enc_get_buffer get_buffer);
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struct radeon_enc_h264_enc_pic {
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enum pipe_h264_enc_picture_type picture_type;
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unsigned frame_num;
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unsigned pic_order_cnt;
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unsigned pic_order_cnt_type;
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unsigned ref_idx_l0;
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unsigned ref_idx_l1;
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unsigned crop_left;
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unsigned crop_right;
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unsigned crop_top;
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unsigned crop_bottom;
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bool not_referenced;
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bool is_idr;
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bool is_even_frame;
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rvcn_enc_task_info_t task_info;
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rvcn_enc_session_init_t session_init;
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rvcn_enc_layer_control_t layer_ctrl;
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rvcn_enc_layer_select_t layer_sel;
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rvcn_enc_h264_slice_control_t slice_ctrl;
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rvcn_enc_h264_spec_misc_t spec_misc;
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rvcn_enc_rate_ctl_session_init_t rc_session_init;
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rvcn_enc_rate_ctl_layer_init_t rc_layer_init;
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rvcn_enc_h264_encode_params_t h264_enc_params;
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rvcn_enc_h264_deblocking_filter_t h264_deblock;
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rvcn_enc_rate_ctl_per_picture_t rc_per_pic;
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rvcn_enc_quality_params_t quality_params;
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rvcn_enc_encode_context_buffer_t ctx_buf;
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rvcn_enc_video_bitstream_buffer_t bit_buf;
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rvcn_enc_feedback_buffer_t fb_buf;
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rvcn_enc_intra_refresh_t intra_ref;
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rvcn_enc_encode_params_t enc_params;
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};
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struct radeon_encoder {
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struct pipe_video_codec base;
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void (*begin)(struct radeon_encoder *enc, struct pipe_h264_enc_picture_desc *pic);
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void (*encode)(struct radeon_encoder *enc);
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void (*destroy)(struct radeon_encoder *enc);
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unsigned stream_handle;
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struct pipe_screen *screen;
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struct radeon_winsys* ws;
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struct radeon_winsys_cs* cs;
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radeon_enc_get_buffer get_buffer;
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struct pb_buffer* handle;
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struct radeon_surf* luma;
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struct radeon_surf* chroma;
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struct pb_buffer* bs_handle;
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unsigned bs_size;
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unsigned cpb_num;
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struct rvid_buffer *si;
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struct rvid_buffer *fb;
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struct rvid_buffer cpb;
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struct radeon_enc_h264_enc_pic enc_pic;
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unsigned alignment;
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unsigned shifter;
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unsigned bits_in_shifter;
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unsigned num_zeros;
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unsigned byte_index;
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unsigned bits_output;
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uint32_t total_task_size;
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uint32_t* p_task_size;
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bool emulation_prevention;
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bool need_feedback;
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};
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void radeon_enc_1_2_init(struct radeon_encoder *enc);
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#endif // _RADEON_VCN_ENC_H
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