/**************************************************************************
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*
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* Copyright 2011 Advanced Micro Devices, Inc.
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* All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the
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* "Software"), to deal in the Software without restriction, including
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* without limitation the rights to use, copy, modify, merge, publish,
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* distribute, sub license, and/or sell copies of the Software, and to
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* permit persons to whom the Software is furnished to do so, subject to
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* the following conditions:
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*
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* The above copyright notice and this permission notice (including the
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* next paragraph) shall be included in all copies or substantial portions
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* of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
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* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
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* IN NO EVENT SHALL THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR
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* ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
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* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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**************************************************************************/
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/*
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* Authors:
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* Christian König <christian.koenig@amd.com>
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*
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*/
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#ifndef RADEON_UVD_H
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#define RADEON_UVD_H
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#include "radeon/radeon_winsys.h"
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#include "vl/vl_video_buffer.h"
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/* UVD uses PM4 packet type 0 and 2 */
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#define RUVD_PKT_TYPE_S(x) (((unsigned)(x) & 0x3) << 30)
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#define RUVD_PKT_TYPE_G(x) (((x) >> 30) & 0x3)
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#define RUVD_PKT_TYPE_C 0x3FFFFFFF
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#define RUVD_PKT_COUNT_S(x) (((unsigned)(x) & 0x3FFF) << 16)
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#define RUVD_PKT_COUNT_G(x) (((x) >> 16) & 0x3FFF)
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#define RUVD_PKT_COUNT_C 0xC000FFFF
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#define RUVD_PKT0_BASE_INDEX_S(x) (((unsigned)(x) & 0xFFFF) << 0)
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#define RUVD_PKT0_BASE_INDEX_G(x) (((x) >> 0) & 0xFFFF)
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#define RUVD_PKT0_BASE_INDEX_C 0xFFFF0000
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#define RUVD_PKT0(index, count) (RUVD_PKT_TYPE_S(0) | RUVD_PKT0_BASE_INDEX_S(index) | RUVD_PKT_COUNT_S(count))
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#define RUVD_PKT2() (RUVD_PKT_TYPE_S(2))
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/* registers involved with UVD */
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#define RUVD_GPCOM_VCPU_CMD 0xEF0C
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#define RUVD_GPCOM_VCPU_DATA0 0xEF10
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#define RUVD_GPCOM_VCPU_DATA1 0xEF14
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#define RUVD_ENGINE_CNTL 0xEF18
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#define RUVD_GPCOM_VCPU_CMD_SOC15 0x2070c
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#define RUVD_GPCOM_VCPU_DATA0_SOC15 0x20710
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#define RUVD_GPCOM_VCPU_DATA1_SOC15 0x20714
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#define RUVD_ENGINE_CNTL_SOC15 0x20718
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/* UVD commands to VCPU */
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#define RUVD_CMD_MSG_BUFFER 0x00000000
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#define RUVD_CMD_DPB_BUFFER 0x00000001
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#define RUVD_CMD_DECODING_TARGET_BUFFER 0x00000002
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#define RUVD_CMD_FEEDBACK_BUFFER 0x00000003
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#define RUVD_CMD_SESSION_CONTEXT_BUFFER 0x00000005
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#define RUVD_CMD_BITSTREAM_BUFFER 0x00000100
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#define RUVD_CMD_ITSCALING_TABLE_BUFFER 0x00000204
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#define RUVD_CMD_CONTEXT_BUFFER 0x00000206
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/* UVD message types */
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#define RUVD_MSG_CREATE 0
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#define RUVD_MSG_DECODE 1
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#define RUVD_MSG_DESTROY 2
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/* UVD stream types */
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#define RUVD_CODEC_H264 0x00000000
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#define RUVD_CODEC_VC1 0x00000001
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#define RUVD_CODEC_MPEG2 0x00000003
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#define RUVD_CODEC_MPEG4 0x00000004
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#define RUVD_CODEC_H264_PERF 0x00000007
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#define RUVD_CODEC_MJPEG 0x00000008
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#define RUVD_CODEC_H265 0x00000010
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/* UVD decode target buffer tiling mode */
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#define RUVD_TILE_LINEAR 0x00000000
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#define RUVD_TILE_8X4 0x00000001
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#define RUVD_TILE_8X8 0x00000002
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#define RUVD_TILE_32AS8 0x00000003
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/* UVD decode target buffer array mode */
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#define RUVD_ARRAY_MODE_LINEAR 0x00000000
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#define RUVD_ARRAY_MODE_MACRO_LINEAR_MICRO_TILED 0x00000001
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#define RUVD_ARRAY_MODE_1D_THIN 0x00000002
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#define RUVD_ARRAY_MODE_2D_THIN 0x00000004
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#define RUVD_ARRAY_MODE_MACRO_TILED_MICRO_LINEAR 0x00000004
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#define RUVD_ARRAY_MODE_MACRO_TILED_MICRO_TILED 0x00000005
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/* UVD tile config */
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#define RUVD_BANK_WIDTH(x) ((x) << 0)
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#define RUVD_BANK_HEIGHT(x) ((x) << 3)
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#define RUVD_MACRO_TILE_ASPECT_RATIO(x) ((x) << 6)
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#define RUVD_NUM_BANKS(x) ((x) << 9)
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/* H.264 profile definitions */
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#define RUVD_H264_PROFILE_BASELINE 0x00000000
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#define RUVD_H264_PROFILE_MAIN 0x00000001
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#define RUVD_H264_PROFILE_HIGH 0x00000002
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#define RUVD_H264_PROFILE_STEREO_HIGH 0x00000003
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#define RUVD_H264_PROFILE_MVC 0x00000004
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/* VC-1 profile definitions */
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#define RUVD_VC1_PROFILE_SIMPLE 0x00000000
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#define RUVD_VC1_PROFILE_MAIN 0x00000001
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#define RUVD_VC1_PROFILE_ADVANCED 0x00000002
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struct ruvd_mvc_element {
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uint16_t viewOrderIndex;
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uint16_t viewId;
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uint16_t numOfAnchorRefsInL0;
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uint16_t viewIdOfAnchorRefsInL0[15];
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uint16_t numOfAnchorRefsInL1;
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uint16_t viewIdOfAnchorRefsInL1[15];
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uint16_t numOfNonAnchorRefsInL0;
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uint16_t viewIdOfNonAnchorRefsInL0[15];
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uint16_t numOfNonAnchorRefsInL1;
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uint16_t viewIdOfNonAnchorRefsInL1[15];
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};
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struct ruvd_h264 {
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uint32_t profile;
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uint32_t level;
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uint32_t sps_info_flags;
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uint32_t pps_info_flags;
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uint8_t chroma_format;
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uint8_t bit_depth_luma_minus8;
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uint8_t bit_depth_chroma_minus8;
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uint8_t log2_max_frame_num_minus4;
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uint8_t pic_order_cnt_type;
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uint8_t log2_max_pic_order_cnt_lsb_minus4;
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uint8_t num_ref_frames;
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uint8_t reserved_8bit;
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int8_t pic_init_qp_minus26;
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int8_t pic_init_qs_minus26;
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int8_t chroma_qp_index_offset;
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int8_t second_chroma_qp_index_offset;
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uint8_t num_slice_groups_minus1;
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uint8_t slice_group_map_type;
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uint8_t num_ref_idx_l0_active_minus1;
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uint8_t num_ref_idx_l1_active_minus1;
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uint16_t slice_group_change_rate_minus1;
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uint16_t reserved_16bit_1;
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uint8_t scaling_list_4x4[6][16];
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uint8_t scaling_list_8x8[2][64];
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uint32_t frame_num;
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uint32_t frame_num_list[16];
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int32_t curr_field_order_cnt_list[2];
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int32_t field_order_cnt_list[16][2];
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uint32_t decoded_pic_idx;
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uint32_t curr_pic_ref_frame_num;
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uint8_t ref_frame_list[16];
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uint32_t reserved[122];
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struct {
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uint32_t numViews;
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uint32_t viewId0;
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struct ruvd_mvc_element mvcElements[1];
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} mvc;
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};
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struct ruvd_h265 {
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uint32_t sps_info_flags;
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uint32_t pps_info_flags;
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uint8_t chroma_format;
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uint8_t bit_depth_luma_minus8;
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uint8_t bit_depth_chroma_minus8;
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uint8_t log2_max_pic_order_cnt_lsb_minus4;
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uint8_t sps_max_dec_pic_buffering_minus1;
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uint8_t log2_min_luma_coding_block_size_minus3;
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uint8_t log2_diff_max_min_luma_coding_block_size;
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uint8_t log2_min_transform_block_size_minus2;
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uint8_t log2_diff_max_min_transform_block_size;
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uint8_t max_transform_hierarchy_depth_inter;
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uint8_t max_transform_hierarchy_depth_intra;
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uint8_t pcm_sample_bit_depth_luma_minus1;
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uint8_t pcm_sample_bit_depth_chroma_minus1;
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uint8_t log2_min_pcm_luma_coding_block_size_minus3;
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uint8_t log2_diff_max_min_pcm_luma_coding_block_size;
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uint8_t num_extra_slice_header_bits;
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uint8_t num_short_term_ref_pic_sets;
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uint8_t num_long_term_ref_pic_sps;
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uint8_t num_ref_idx_l0_default_active_minus1;
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uint8_t num_ref_idx_l1_default_active_minus1;
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int8_t pps_cb_qp_offset;
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int8_t pps_cr_qp_offset;
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int8_t pps_beta_offset_div2;
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int8_t pps_tc_offset_div2;
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uint8_t diff_cu_qp_delta_depth;
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uint8_t num_tile_columns_minus1;
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uint8_t num_tile_rows_minus1;
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uint8_t log2_parallel_merge_level_minus2;
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uint16_t column_width_minus1[19];
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uint16_t row_height_minus1[21];
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int8_t init_qp_minus26;
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uint8_t num_delta_pocs_ref_rps_idx;
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uint8_t curr_idx;
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uint8_t reserved1;
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int32_t curr_poc;
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uint8_t ref_pic_list[16];
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int32_t poc_list[16];
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uint8_t ref_pic_set_st_curr_before[8];
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uint8_t ref_pic_set_st_curr_after[8];
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uint8_t ref_pic_set_lt_curr[8];
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uint8_t ucScalingListDCCoefSizeID2[6];
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uint8_t ucScalingListDCCoefSizeID3[2];
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uint8_t highestTid;
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uint8_t isNonRef;
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uint8_t p010_mode;
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uint8_t msb_mode;
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uint8_t luma_10to8;
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uint8_t chroma_10to8;
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uint8_t sclr_luma10to8;
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uint8_t sclr_chroma10to8;
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uint8_t direct_reflist[2][15];
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};
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struct ruvd_vc1 {
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uint32_t profile;
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uint32_t level;
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uint32_t sps_info_flags;
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uint32_t pps_info_flags;
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uint32_t pic_structure;
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uint32_t chroma_format;
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};
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struct ruvd_mpeg2 {
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uint32_t decoded_pic_idx;
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uint32_t ref_pic_idx[2];
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uint8_t load_intra_quantiser_matrix;
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uint8_t load_nonintra_quantiser_matrix;
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uint8_t reserved_quantiser_alignement[2];
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uint8_t intra_quantiser_matrix[64];
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uint8_t nonintra_quantiser_matrix[64];
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uint8_t profile_and_level_indication;
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uint8_t chroma_format;
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uint8_t picture_coding_type;
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uint8_t reserved_1;
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uint8_t f_code[2][2];
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uint8_t intra_dc_precision;
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uint8_t pic_structure;
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uint8_t top_field_first;
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uint8_t frame_pred_frame_dct;
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uint8_t concealment_motion_vectors;
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uint8_t q_scale_type;
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uint8_t intra_vlc_format;
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uint8_t alternate_scan;
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};
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struct ruvd_mpeg4
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{
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uint32_t decoded_pic_idx;
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uint32_t ref_pic_idx[2];
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uint32_t variant_type;
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uint8_t profile_and_level_indication;
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uint8_t video_object_layer_verid;
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uint8_t video_object_layer_shape;
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uint8_t reserved_1;
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uint16_t video_object_layer_width;
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uint16_t video_object_layer_height;
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uint16_t vop_time_increment_resolution;
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uint16_t reserved_2;
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uint32_t flags;
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uint8_t quant_type;
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uint8_t reserved_3[3];
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uint8_t intra_quant_mat[64];
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uint8_t nonintra_quant_mat[64];
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struct {
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uint8_t sprite_enable;
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uint8_t reserved_4[3];
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uint16_t sprite_width;
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uint16_t sprite_height;
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int16_t sprite_left_coordinate;
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int16_t sprite_top_coordinate;
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uint8_t no_of_sprite_warping_points;
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uint8_t sprite_warping_accuracy;
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uint8_t sprite_brightness_change;
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uint8_t low_latency_sprite_enable;
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} sprite_config;
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struct {
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uint32_t flags;
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uint8_t vol_mode;
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uint8_t reserved_5[3];
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} divx_311_config;
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};
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/* message between driver and hardware */
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struct ruvd_msg {
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uint32_t size;
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uint32_t msg_type;
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uint32_t stream_handle;
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uint32_t status_report_feedback_number;
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union {
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struct {
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uint32_t stream_type;
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uint32_t session_flags;
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uint32_t asic_id;
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uint32_t width_in_samples;
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uint32_t height_in_samples;
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uint32_t dpb_buffer;
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uint32_t dpb_size;
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uint32_t dpb_model;
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uint32_t version_info;
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} create;
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struct {
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uint32_t stream_type;
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uint32_t decode_flags;
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uint32_t width_in_samples;
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uint32_t height_in_samples;
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uint32_t dpb_buffer;
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uint32_t dpb_size;
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uint32_t dpb_model;
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uint32_t dpb_reserved;
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uint32_t db_offset_alignment;
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uint32_t db_pitch;
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uint32_t db_tiling_mode;
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uint32_t db_array_mode;
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uint32_t db_field_mode;
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uint32_t db_surf_tile_config;
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uint32_t db_aligned_height;
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uint32_t db_reserved;
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uint32_t use_addr_macro;
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uint32_t bsd_buffer;
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uint32_t bsd_size;
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uint32_t pic_param_buffer;
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uint32_t pic_param_size;
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uint32_t mb_cntl_buffer;
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uint32_t mb_cntl_size;
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uint32_t dt_buffer;
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uint32_t dt_pitch;
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uint32_t dt_tiling_mode;
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uint32_t dt_array_mode;
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uint32_t dt_field_mode;
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uint32_t dt_luma_top_offset;
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uint32_t dt_luma_bottom_offset;
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uint32_t dt_chroma_top_offset;
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uint32_t dt_chroma_bottom_offset;
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uint32_t dt_surf_tile_config;
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uint32_t dt_uv_surf_tile_config;
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// re-use dt_wa_chroma_top_offset as dt_ext_info for UV pitch in stoney
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uint32_t dt_wa_chroma_top_offset;
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uint32_t dt_wa_chroma_bottom_offset;
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uint32_t reserved[16];
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union {
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struct ruvd_h264 h264;
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struct ruvd_h265 h265;
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struct ruvd_vc1 vc1;
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struct ruvd_mpeg2 mpeg2;
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struct ruvd_mpeg4 mpeg4;
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uint32_t info[768];
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} codec;
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uint8_t extension_support;
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uint8_t reserved_8bit_1;
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uint8_t reserved_8bit_2;
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uint8_t reserved_8bit_3;
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uint32_t extension_reserved[64];
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} decode;
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} body;
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};
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/* driver dependent callback */
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typedef struct pb_buffer* (*ruvd_set_dtb)
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(struct ruvd_msg* msg, struct vl_video_buffer *vb);
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/* create an UVD decode */
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struct pipe_video_codec *ruvd_create_decoder(struct pipe_context *context,
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const struct pipe_video_codec *templat,
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ruvd_set_dtb set_dtb);
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/* fill decoding target field from the luma and chroma surfaces */
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void ruvd_set_dt_surfaces(struct ruvd_msg *msg, struct radeon_surf *luma,
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struct radeon_surf *chroma);
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#endif
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