/*
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* Copyright 2013 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*
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* Authors: Marek Olšák <maraeo@gmail.com>
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*
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*/
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#include "r600_pipe_common.h"
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#include "r600_cs.h"
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#include "util/u_memory.h"
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#include "evergreend.h"
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#define R_008490_CP_STRMOUT_CNTL 0x008490
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#define R_028AB0_VGT_STRMOUT_EN 0x028AB0
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#define R_028B20_VGT_STRMOUT_BUFFER_EN 0x028B20
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static void r600_set_streamout_enable(struct r600_common_context *rctx, bool enable);
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static struct pipe_stream_output_target *
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r600_create_so_target(struct pipe_context *ctx,
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struct pipe_resource *buffer,
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unsigned buffer_offset,
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unsigned buffer_size)
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{
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struct r600_common_context *rctx = (struct r600_common_context *)ctx;
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struct r600_so_target *t;
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struct r600_resource *rbuffer = (struct r600_resource*)buffer;
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t = CALLOC_STRUCT(r600_so_target);
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if (!t) {
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return NULL;
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}
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u_suballocator_alloc(rctx->allocator_zeroed_memory, 4, 4,
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&t->buf_filled_size_offset,
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(struct pipe_resource**)&t->buf_filled_size);
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if (!t->buf_filled_size) {
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FREE(t);
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return NULL;
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}
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t->b.reference.count = 1;
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t->b.context = ctx;
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pipe_resource_reference(&t->b.buffer, buffer);
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t->b.buffer_offset = buffer_offset;
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t->b.buffer_size = buffer_size;
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util_range_add(&rbuffer->valid_buffer_range, buffer_offset,
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buffer_offset + buffer_size);
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return &t->b;
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}
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static void r600_so_target_destroy(struct pipe_context *ctx,
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struct pipe_stream_output_target *target)
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{
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struct r600_so_target *t = (struct r600_so_target*)target;
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pipe_resource_reference(&t->b.buffer, NULL);
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r600_resource_reference(&t->buf_filled_size, NULL);
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FREE(t);
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}
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void r600_streamout_buffers_dirty(struct r600_common_context *rctx)
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{
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struct r600_atom *begin = &rctx->streamout.begin_atom;
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unsigned num_bufs = util_bitcount(rctx->streamout.enabled_mask);
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unsigned num_bufs_appended = util_bitcount(rctx->streamout.enabled_mask &
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rctx->streamout.append_bitmask);
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if (!num_bufs)
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return;
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rctx->streamout.num_dw_for_end =
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12 + /* flush_vgt_streamout */
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num_bufs * 11; /* STRMOUT_BUFFER_UPDATE, BUFFER_SIZE */
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begin->num_dw = 12; /* flush_vgt_streamout */
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begin->num_dw += num_bufs * 7; /* SET_CONTEXT_REG */
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if (rctx->family >= CHIP_RS780 && rctx->family <= CHIP_RV740)
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begin->num_dw += num_bufs * 5; /* STRMOUT_BASE_UPDATE */
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begin->num_dw +=
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num_bufs_appended * 8 + /* STRMOUT_BUFFER_UPDATE */
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(num_bufs - num_bufs_appended) * 6 + /* STRMOUT_BUFFER_UPDATE */
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(rctx->family > CHIP_R600 && rctx->family < CHIP_RS780 ? 2 : 0); /* SURFACE_BASE_UPDATE */
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rctx->set_atom_dirty(rctx, begin, true);
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r600_set_streamout_enable(rctx, true);
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}
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void r600_set_streamout_targets(struct pipe_context *ctx,
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unsigned num_targets,
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struct pipe_stream_output_target **targets,
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const unsigned *offsets)
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{
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struct r600_common_context *rctx = (struct r600_common_context *)ctx;
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unsigned i;
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unsigned enabled_mask = 0, append_bitmask = 0;
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/* Stop streamout. */
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if (rctx->streamout.num_targets && rctx->streamout.begin_emitted) {
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r600_emit_streamout_end(rctx);
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}
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/* Set the new targets. */
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for (i = 0; i < num_targets; i++) {
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pipe_so_target_reference((struct pipe_stream_output_target**)&rctx->streamout.targets[i], targets[i]);
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if (!targets[i])
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continue;
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r600_context_add_resource_size(ctx, targets[i]->buffer);
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enabled_mask |= 1 << i;
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if (offsets[i] == ((unsigned)-1))
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append_bitmask |= 1 << i;
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}
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for (; i < rctx->streamout.num_targets; i++) {
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pipe_so_target_reference((struct pipe_stream_output_target**)&rctx->streamout.targets[i], NULL);
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}
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rctx->streamout.enabled_mask = enabled_mask;
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rctx->streamout.num_targets = num_targets;
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rctx->streamout.append_bitmask = append_bitmask;
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if (num_targets) {
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r600_streamout_buffers_dirty(rctx);
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} else {
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rctx->set_atom_dirty(rctx, &rctx->streamout.begin_atom, false);
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r600_set_streamout_enable(rctx, false);
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}
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}
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static void r600_flush_vgt_streamout(struct r600_common_context *rctx)
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{
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struct radeon_winsys_cs *cs = rctx->gfx.cs;
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unsigned reg_strmout_cntl;
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/* The register is at different places on different ASICs. */
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if (rctx->chip_class >= EVERGREEN) {
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reg_strmout_cntl = R_0084FC_CP_STRMOUT_CNTL;
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} else {
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reg_strmout_cntl = R_008490_CP_STRMOUT_CNTL;
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}
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radeon_set_config_reg(cs, reg_strmout_cntl, 0);
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radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
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radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_SO_VGTSTREAMOUT_FLUSH) | EVENT_INDEX(0));
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radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, 0));
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radeon_emit(cs, WAIT_REG_MEM_EQUAL); /* wait until the register is equal to the reference value */
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radeon_emit(cs, reg_strmout_cntl >> 2); /* register */
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radeon_emit(cs, 0);
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radeon_emit(cs, S_0084FC_OFFSET_UPDATE_DONE(1)); /* reference value */
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radeon_emit(cs, S_0084FC_OFFSET_UPDATE_DONE(1)); /* mask */
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radeon_emit(cs, 4); /* poll interval */
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}
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static void r600_emit_streamout_begin(struct r600_common_context *rctx, struct r600_atom *atom)
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{
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struct radeon_winsys_cs *cs = rctx->gfx.cs;
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struct r600_so_target **t = rctx->streamout.targets;
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uint16_t *stride_in_dw = rctx->streamout.stride_in_dw;
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unsigned i, update_flags = 0;
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r600_flush_vgt_streamout(rctx);
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for (i = 0; i < rctx->streamout.num_targets; i++) {
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if (!t[i])
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continue;
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t[i]->stride_in_dw = stride_in_dw[i];
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uint64_t va = r600_resource(t[i]->b.buffer)->gpu_address;
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update_flags |= SURFACE_BASE_UPDATE_STRMOUT(i);
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radeon_set_context_reg_seq(cs, R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0 + 16*i, 3);
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radeon_emit(cs, (t[i]->b.buffer_offset +
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t[i]->b.buffer_size) >> 2); /* BUFFER_SIZE (in DW) */
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radeon_emit(cs, stride_in_dw[i]); /* VTX_STRIDE (in DW) */
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radeon_emit(cs, va >> 8); /* BUFFER_BASE */
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r600_emit_reloc(rctx, &rctx->gfx, r600_resource(t[i]->b.buffer),
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RADEON_USAGE_WRITE, RADEON_PRIO_SHADER_RW_BUFFER);
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/* R7xx requires this packet after updating BUFFER_BASE.
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* Without this, R7xx locks up. */
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if (rctx->family >= CHIP_RS780 && rctx->family <= CHIP_RV740) {
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radeon_emit(cs, PKT3(PKT3_STRMOUT_BASE_UPDATE, 1, 0));
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radeon_emit(cs, i);
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radeon_emit(cs, va >> 8);
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r600_emit_reloc(rctx, &rctx->gfx, r600_resource(t[i]->b.buffer),
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RADEON_USAGE_WRITE, RADEON_PRIO_SHADER_RW_BUFFER);
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}
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if (rctx->streamout.append_bitmask & (1 << i) && t[i]->buf_filled_size_valid) {
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uint64_t va = t[i]->buf_filled_size->gpu_address +
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t[i]->buf_filled_size_offset;
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/* Append. */
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radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
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radeon_emit(cs, STRMOUT_SELECT_BUFFER(i) |
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STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_FROM_MEM)); /* control */
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radeon_emit(cs, 0); /* unused */
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radeon_emit(cs, 0); /* unused */
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radeon_emit(cs, va); /* src address lo */
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radeon_emit(cs, va >> 32); /* src address hi */
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r600_emit_reloc(rctx, &rctx->gfx, t[i]->buf_filled_size,
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RADEON_USAGE_READ, RADEON_PRIO_SO_FILLED_SIZE);
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} else {
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/* Start from the beginning. */
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radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
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radeon_emit(cs, STRMOUT_SELECT_BUFFER(i) |
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STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_FROM_PACKET)); /* control */
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radeon_emit(cs, 0); /* unused */
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radeon_emit(cs, 0); /* unused */
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radeon_emit(cs, t[i]->b.buffer_offset >> 2); /* buffer offset in DW */
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radeon_emit(cs, 0); /* unused */
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}
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}
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if (rctx->family > CHIP_R600 && rctx->family < CHIP_RV770) {
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radeon_emit(cs, PKT3(PKT3_SURFACE_BASE_UPDATE, 0, 0));
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radeon_emit(cs, update_flags);
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}
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rctx->streamout.begin_emitted = true;
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}
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void r600_emit_streamout_end(struct r600_common_context *rctx)
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{
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struct radeon_winsys_cs *cs = rctx->gfx.cs;
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struct r600_so_target **t = rctx->streamout.targets;
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unsigned i;
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uint64_t va;
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r600_flush_vgt_streamout(rctx);
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for (i = 0; i < rctx->streamout.num_targets; i++) {
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if (!t[i])
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continue;
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va = t[i]->buf_filled_size->gpu_address + t[i]->buf_filled_size_offset;
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radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
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radeon_emit(cs, STRMOUT_SELECT_BUFFER(i) |
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STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_NONE) |
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STRMOUT_STORE_BUFFER_FILLED_SIZE); /* control */
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radeon_emit(cs, va); /* dst address lo */
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radeon_emit(cs, va >> 32); /* dst address hi */
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radeon_emit(cs, 0); /* unused */
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radeon_emit(cs, 0); /* unused */
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r600_emit_reloc(rctx, &rctx->gfx, t[i]->buf_filled_size,
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RADEON_USAGE_WRITE, RADEON_PRIO_SO_FILLED_SIZE);
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/* Zero the buffer size. The counters (primitives generated,
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* primitives emitted) may be enabled even if there is not
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* buffer bound. This ensures that the primitives-emitted query
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* won't increment. */
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radeon_set_context_reg(cs, R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0 + 16*i, 0);
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t[i]->buf_filled_size_valid = true;
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}
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rctx->streamout.begin_emitted = false;
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rctx->flags |= R600_CONTEXT_STREAMOUT_FLUSH;
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}
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/* STREAMOUT CONFIG DERIVED STATE
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*
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* Streamout must be enabled for the PRIMITIVES_GENERATED query to work.
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* The buffer mask is an independent state, so no writes occur if there
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* are no buffers bound.
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*/
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static void r600_emit_streamout_enable(struct r600_common_context *rctx,
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struct r600_atom *atom)
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{
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unsigned strmout_config_reg = R_028AB0_VGT_STRMOUT_EN;
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unsigned strmout_config_val = S_028B94_STREAMOUT_0_EN(r600_get_strmout_en(rctx));
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unsigned strmout_buffer_reg = R_028B20_VGT_STRMOUT_BUFFER_EN;
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unsigned strmout_buffer_val = rctx->streamout.hw_enabled_mask &
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rctx->streamout.enabled_stream_buffers_mask;
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if (rctx->chip_class >= EVERGREEN) {
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strmout_buffer_reg = R_028B98_VGT_STRMOUT_BUFFER_CONFIG;
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strmout_config_reg = R_028B94_VGT_STRMOUT_CONFIG;
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strmout_config_val |=
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S_028B94_STREAMOUT_1_EN(r600_get_strmout_en(rctx)) |
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S_028B94_STREAMOUT_2_EN(r600_get_strmout_en(rctx)) |
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S_028B94_STREAMOUT_3_EN(r600_get_strmout_en(rctx));
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}
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radeon_set_context_reg(rctx->gfx.cs, strmout_buffer_reg, strmout_buffer_val);
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radeon_set_context_reg(rctx->gfx.cs, strmout_config_reg, strmout_config_val);
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}
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static void r600_set_streamout_enable(struct r600_common_context *rctx, bool enable)
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{
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bool old_strmout_en = r600_get_strmout_en(rctx);
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unsigned old_hw_enabled_mask = rctx->streamout.hw_enabled_mask;
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rctx->streamout.streamout_enabled = enable;
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rctx->streamout.hw_enabled_mask = rctx->streamout.enabled_mask |
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(rctx->streamout.enabled_mask << 4) |
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(rctx->streamout.enabled_mask << 8) |
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(rctx->streamout.enabled_mask << 12);
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if ((old_strmout_en != r600_get_strmout_en(rctx)) ||
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(old_hw_enabled_mask != rctx->streamout.hw_enabled_mask)) {
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rctx->set_atom_dirty(rctx, &rctx->streamout.enable_atom, true);
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}
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}
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void r600_update_prims_generated_query_state(struct r600_common_context *rctx,
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unsigned type, int diff)
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{
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if (type == PIPE_QUERY_PRIMITIVES_GENERATED) {
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bool old_strmout_en = r600_get_strmout_en(rctx);
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rctx->streamout.num_prims_gen_queries += diff;
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assert(rctx->streamout.num_prims_gen_queries >= 0);
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rctx->streamout.prims_gen_query_enabled =
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rctx->streamout.num_prims_gen_queries != 0;
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if (old_strmout_en != r600_get_strmout_en(rctx)) {
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rctx->set_atom_dirty(rctx, &rctx->streamout.enable_atom, true);
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}
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}
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}
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void r600_streamout_init(struct r600_common_context *rctx)
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{
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rctx->b.create_stream_output_target = r600_create_so_target;
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rctx->b.stream_output_target_destroy = r600_so_target_destroy;
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rctx->streamout.begin_atom.emit = r600_emit_streamout_begin;
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rctx->streamout.enable_atom.emit = r600_emit_streamout_enable;
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rctx->streamout.enable_atom.num_dw = 6;
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}
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