#ifndef R600_FORMATS_H
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#define R600_FORMATS_H
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#include "util/u_format.h"
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#include "r600_pipe.h"
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/* list of formats from R700 ISA document - apply across GPUs in different registers */
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#define FMT_INVALID 0x00000000
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#define FMT_8 0x00000001
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#define FMT_4_4 0x00000002
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#define FMT_3_3_2 0x00000003
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#define FMT_16 0x00000005
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#define FMT_16_FLOAT 0x00000006
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#define FMT_8_8 0x00000007
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#define FMT_5_6_5 0x00000008
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#define FMT_6_5_5 0x00000009
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#define FMT_1_5_5_5 0x0000000A
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#define FMT_4_4_4_4 0x0000000B
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#define FMT_5_5_5_1 0x0000000C
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#define FMT_32 0x0000000D
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#define FMT_32_FLOAT 0x0000000E
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#define FMT_16_16 0x0000000F
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#define FMT_16_16_FLOAT 0x00000010
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#define FMT_8_24 0x00000011
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#define FMT_8_24_FLOAT 0x00000012
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#define FMT_24_8 0x00000013
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#define FMT_24_8_FLOAT 0x00000014
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#define FMT_10_11_11 0x00000015
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#define FMT_10_11_11_FLOAT 0x00000016
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#define FMT_11_11_10 0x00000017
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#define FMT_11_11_10_FLOAT 0x00000018
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#define FMT_2_10_10_10 0x00000019
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#define FMT_8_8_8_8 0x0000001A
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#define FMT_10_10_10_2 0x0000001B
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#define FMT_X24_8_32_FLOAT 0x0000001C
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#define FMT_32_32 0x0000001D
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#define FMT_32_32_FLOAT 0x0000001E
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#define FMT_16_16_16_16 0x0000001F
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#define FMT_16_16_16_16_FLOAT 0x00000020
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#define FMT_32_32_32_32 0x00000022
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#define FMT_32_32_32_32_FLOAT 0x00000023
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#define FMT_1 0x00000025
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#define FMT_GB_GR 0x00000027
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#define FMT_BG_RG 0x00000028
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#define FMT_32_AS_8 0x00000029
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#define FMT_32_AS_8_8 0x0000002a
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#define FMT_5_9_9_9_SHAREDEXP 0x0000002b
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#define FMT_8_8_8 0x0000002c
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#define FMT_16_16_16 0x0000002d
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#define FMT_16_16_16_FLOAT 0x0000002e
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#define FMT_32_32_32 0x0000002f
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#define FMT_32_32_32_FLOAT 0x00000030
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#define FMT_BC1 0x00000031
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#define FMT_BC2 0x00000032
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#define FMT_BC3 0x00000033
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#define FMT_BC4 0x00000034
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#define FMT_BC5 0x00000035
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#define FMT_BC6 0x00000036
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#define FMT_BC7 0x00000037
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#define FMT_32_AS_32_32_32_32 0x00000038
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#define ENDIAN_NONE 0
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#define ENDIAN_8IN16 1
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#define ENDIAN_8IN32 2
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#define ENDIAN_8IN64 3
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static inline unsigned r600_endian_swap(unsigned size)
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{
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if (R600_BIG_ENDIAN) {
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switch (size) {
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case 64:
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return ENDIAN_8IN64;
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case 32:
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return ENDIAN_8IN32;
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case 16:
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return ENDIAN_8IN16;
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default:
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return ENDIAN_NONE;
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}
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} else {
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return ENDIAN_NONE;
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}
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}
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static inline bool r600_is_vertex_format_supported(enum pipe_format format)
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{
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const struct util_format_description *desc = util_format_description(format);
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unsigned i;
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if (format == PIPE_FORMAT_R11G11B10_FLOAT)
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return true;
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if (!desc)
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return false;
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/* Find the first non-VOID channel. */
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for (i = 0; i < 4; i++) {
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if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID)
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break;
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}
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if (i == 4)
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return false;
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/* No fixed, no double. */
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if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN ||
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(desc->channel[i].size == 64 &&
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desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT) ||
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desc->channel[i].type == UTIL_FORMAT_TYPE_FIXED)
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return false;
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/* No scaled/norm formats with 32 bits per channel. */
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if (desc->channel[i].size == 32 &&
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!desc->channel[i].pure_integer &&
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(desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED ||
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desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED))
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return false;
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return true;
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}
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#endif
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