/*
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* Copyright (C) 2009 Nicolai Haehnle.
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*
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* All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining
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* a copy of this software and associated documentation files (the
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* "Software"), to deal in the Software without restriction, including
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* without limitation the rights to use, copy, modify, merge, publish,
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* distribute, sublicense, and/or sell copies of the Software, and to
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* permit persons to whom the Software is furnished to do so, subject to
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* the following conditions:
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*
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* The above copyright notice and this permission notice (including the
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* next paragraph) shall be included in all copies or substantial
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* portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
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* IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
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* LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
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* OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
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* WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#include "radeon_program_pair.h"
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#include "radeon_compiler.h"
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#include "radeon_compiler_util.h"
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/**
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* Finally rewrite ADD, MOV, MUL as the appropriate native instruction
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* and reverse the order of arguments for CMP.
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*/
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static void final_rewrite(struct rc_sub_instruction *inst)
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{
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struct rc_src_register tmp;
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switch(inst->Opcode) {
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case RC_OPCODE_ADD:
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inst->SrcReg[2] = inst->SrcReg[1];
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inst->SrcReg[1].File = RC_FILE_NONE;
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inst->SrcReg[1].Swizzle = RC_SWIZZLE_1111;
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inst->SrcReg[1].Negate = RC_MASK_NONE;
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inst->Opcode = RC_OPCODE_MAD;
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break;
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case RC_OPCODE_CMP:
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tmp = inst->SrcReg[2];
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inst->SrcReg[2] = inst->SrcReg[0];
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inst->SrcReg[0] = tmp;
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break;
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case RC_OPCODE_MOV:
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/* AMD say we should use CMP.
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* However, when we transform
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* KIL -r0;
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* into
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* CMP tmp, -r0, -r0, 0;
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* KIL tmp;
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* we get incorrect behaviour on R500 when r0 == 0.0.
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* It appears that the R500 KIL hardware treats -0.0 as less
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* than zero.
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*/
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inst->SrcReg[1].File = RC_FILE_NONE;
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inst->SrcReg[1].Swizzle = RC_SWIZZLE_1111;
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inst->SrcReg[2].File = RC_FILE_NONE;
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inst->SrcReg[2].Swizzle = RC_SWIZZLE_0000;
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inst->Opcode = RC_OPCODE_MAD;
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break;
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case RC_OPCODE_MUL:
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inst->SrcReg[2].File = RC_FILE_NONE;
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inst->SrcReg[2].Swizzle = RC_SWIZZLE_0000;
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inst->Opcode = RC_OPCODE_MAD;
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break;
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default:
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/* nothing to do */
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break;
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}
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}
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/**
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* Classify an instruction according to which ALUs etc. it needs
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*/
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static void classify_instruction(struct rc_sub_instruction * inst,
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int * needrgb, int * needalpha, int * istranscendent)
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{
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*needrgb = (inst->DstReg.WriteMask & RC_MASK_XYZ) ? 1 : 0;
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*needalpha = (inst->DstReg.WriteMask & RC_MASK_W) ? 1 : 0;
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*istranscendent = 0;
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if (inst->WriteALUResult == RC_ALURESULT_X)
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*needrgb = 1;
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else if (inst->WriteALUResult == RC_ALURESULT_W)
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*needalpha = 1;
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switch(inst->Opcode) {
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case RC_OPCODE_ADD:
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case RC_OPCODE_CMP:
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case RC_OPCODE_CND:
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case RC_OPCODE_DDX:
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case RC_OPCODE_DDY:
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case RC_OPCODE_FRC:
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case RC_OPCODE_MAD:
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case RC_OPCODE_MAX:
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case RC_OPCODE_MIN:
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case RC_OPCODE_MOV:
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case RC_OPCODE_MUL:
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break;
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case RC_OPCODE_COS:
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case RC_OPCODE_EX2:
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case RC_OPCODE_LG2:
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case RC_OPCODE_RCP:
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case RC_OPCODE_RSQ:
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case RC_OPCODE_SIN:
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*istranscendent = 1;
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*needalpha = 1;
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break;
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case RC_OPCODE_DP4:
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*needalpha = 1;
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/* fall through */
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case RC_OPCODE_DP3:
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*needrgb = 1;
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break;
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default:
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break;
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}
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}
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static void src_uses(struct rc_src_register src, unsigned int * rgb,
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unsigned int * alpha)
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{
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int j;
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for(j = 0; j < 4; ++j) {
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unsigned int swz = GET_SWZ(src.Swizzle, j);
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if (swz < 3)
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*rgb = 1;
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else if (swz < 4)
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*alpha = 1;
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}
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}
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/**
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* Fill the given ALU instruction's opcodes and source operands into the given pair,
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* if possible.
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*/
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static void set_pair_instruction(struct r300_fragment_program_compiler *c,
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struct rc_pair_instruction * pair,
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struct rc_sub_instruction * inst)
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{
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int needrgb, needalpha, istranscendent;
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const struct rc_opcode_info * opcode;
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int i;
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memset(pair, 0, sizeof(struct rc_pair_instruction));
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classify_instruction(inst, &needrgb, &needalpha, &istranscendent);
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if (needrgb) {
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if (istranscendent)
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pair->RGB.Opcode = RC_OPCODE_REPL_ALPHA;
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else
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pair->RGB.Opcode = inst->Opcode;
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if (inst->SaturateMode == RC_SATURATE_ZERO_ONE)
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pair->RGB.Saturate = 1;
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}
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if (needalpha) {
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pair->Alpha.Opcode = inst->Opcode;
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if (inst->SaturateMode == RC_SATURATE_ZERO_ONE)
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pair->Alpha.Saturate = 1;
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}
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opcode = rc_get_opcode_info(inst->Opcode);
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/* Presubtract handling:
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* We need to make sure that the values used by the presubtract
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* operation end up in src0 or src1. */
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if(inst->PreSub.Opcode != RC_PRESUB_NONE) {
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/* rc_pair_alloc_source() will fill in data for
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* pair->{RGB,ALPHA}.Src[RC_PAIR_PRESUB_SRC] */
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int j;
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for(j = 0; j < 3; j++) {
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int src_regs;
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if(inst->SrcReg[j].File != RC_FILE_PRESUB)
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continue;
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src_regs = rc_presubtract_src_reg_count(
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inst->PreSub.Opcode);
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for(i = 0; i < src_regs; i++) {
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unsigned int rgb = 0;
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unsigned int alpha = 0;
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src_uses(inst->SrcReg[j], &rgb, &alpha);
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if(rgb) {
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pair->RGB.Src[i].File =
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inst->PreSub.SrcReg[i].File;
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pair->RGB.Src[i].Index =
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inst->PreSub.SrcReg[i].Index;
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pair->RGB.Src[i].Used = 1;
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}
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if(alpha) {
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pair->Alpha.Src[i].File =
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inst->PreSub.SrcReg[i].File;
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pair->Alpha.Src[i].Index =
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inst->PreSub.SrcReg[i].Index;
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pair->Alpha.Src[i].Used = 1;
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}
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}
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}
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}
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for(i = 0; i < opcode->NumSrcRegs; ++i) {
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int source;
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if (needrgb && !istranscendent) {
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unsigned int srcrgb = 0;
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unsigned int srcalpha = 0;
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unsigned int srcmask = 0;
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int j;
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/* We don't care about the alpha channel here. We only
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* want the part of the swizzle that writes to rgb,
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* since we are creating an rgb instruction. */
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for(j = 0; j < 3; ++j) {
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unsigned int swz = GET_SWZ(inst->SrcReg[i].Swizzle, j);
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if (swz < RC_SWIZZLE_W)
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srcrgb = 1;
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else if (swz == RC_SWIZZLE_W)
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srcalpha = 1;
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if (swz < RC_SWIZZLE_UNUSED)
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srcmask |= 1 << j;
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}
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source = rc_pair_alloc_source(pair, srcrgb, srcalpha,
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inst->SrcReg[i].File, inst->SrcReg[i].Index);
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if (source < 0) {
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rc_error(&c->Base, "Failed to translate "
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"rgb instruction.\n");
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return;
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}
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pair->RGB.Arg[i].Source = source;
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pair->RGB.Arg[i].Swizzle =
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rc_init_swizzle(inst->SrcReg[i].Swizzle, 3);
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pair->RGB.Arg[i].Abs = inst->SrcReg[i].Abs;
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pair->RGB.Arg[i].Negate = !!(srcmask & inst->SrcReg[i].Negate & (RC_MASK_X | RC_MASK_Y | RC_MASK_Z));
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}
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if (needalpha) {
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unsigned int srcrgb = 0;
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unsigned int srcalpha = 0;
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unsigned int swz;
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if (istranscendent) {
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swz = rc_get_scalar_src_swz(inst->SrcReg[i].Swizzle);
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} else {
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swz = GET_SWZ(inst->SrcReg[i].Swizzle, 3);
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}
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if (swz < 3)
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srcrgb = 1;
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else if (swz < 4)
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srcalpha = 1;
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source = rc_pair_alloc_source(pair, srcrgb, srcalpha,
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inst->SrcReg[i].File, inst->SrcReg[i].Index);
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if (source < 0) {
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rc_error(&c->Base, "Failed to translate "
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"alpha instruction.\n");
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return;
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}
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pair->Alpha.Arg[i].Source = source;
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pair->Alpha.Arg[i].Swizzle = rc_init_swizzle(swz, 1);
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pair->Alpha.Arg[i].Abs = inst->SrcReg[i].Abs;
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if (istranscendent) {
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pair->Alpha.Arg[i].Negate =
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!!(inst->SrcReg[i].Negate &
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inst->DstReg.WriteMask);
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} else {
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pair->Alpha.Arg[i].Negate =
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!!(inst->SrcReg[i].Negate & RC_MASK_W);
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}
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}
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}
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/* Destination handling */
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if (inst->DstReg.File == RC_FILE_OUTPUT) {
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if (inst->DstReg.Index == c->OutputDepth) {
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pair->Alpha.DepthWriteMask |= GET_BIT(inst->DstReg.WriteMask, 3);
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} else {
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for (i = 0; i < 4; i++) {
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if (inst->DstReg.Index == c->OutputColor[i]) {
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pair->RGB.Target = i;
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pair->Alpha.Target = i;
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pair->RGB.OutputWriteMask |=
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inst->DstReg.WriteMask & RC_MASK_XYZ;
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pair->Alpha.OutputWriteMask |=
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GET_BIT(inst->DstReg.WriteMask, 3);
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break;
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}
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}
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}
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} else {
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if (needrgb) {
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pair->RGB.DestIndex = inst->DstReg.Index;
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pair->RGB.WriteMask |= inst->DstReg.WriteMask & RC_MASK_XYZ;
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}
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if (needalpha) {
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pair->Alpha.WriteMask |= (GET_BIT(inst->DstReg.WriteMask, 3) << 3);
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if (pair->Alpha.WriteMask) {
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pair->Alpha.DestIndex = inst->DstReg.Index;
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}
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}
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}
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if (needrgb) {
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pair->RGB.Omod = inst->Omod;
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}
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if (needalpha) {
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pair->Alpha.Omod = inst->Omod;
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}
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if (inst->WriteALUResult) {
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pair->WriteALUResult = inst->WriteALUResult;
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pair->ALUResultCompare = inst->ALUResultCompare;
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}
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}
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static void check_opcode_support(struct r300_fragment_program_compiler *c,
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struct rc_sub_instruction *inst)
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{
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const struct rc_opcode_info * opcode = rc_get_opcode_info(inst->Opcode);
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if (opcode->HasDstReg) {
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if (inst->SaturateMode == RC_SATURATE_MINUS_PLUS_ONE) {
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rc_error(&c->Base, "Fragment program does not support signed Saturate.\n");
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return;
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}
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}
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for (unsigned i = 0; i < opcode->NumSrcRegs; i++) {
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if (inst->SrcReg[i].RelAddr) {
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rc_error(&c->Base, "Fragment program does not support relative addressing "
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" of source operands.\n");
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return;
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}
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}
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}
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/**
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* Translate all ALU instructions into corresponding pair instructions,
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* performing no other changes.
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*/
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void rc_pair_translate(struct radeon_compiler *cc, void *user)
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{
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struct r300_fragment_program_compiler *c = (struct r300_fragment_program_compiler*)cc;
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for(struct rc_instruction * inst = c->Base.Program.Instructions.Next;
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inst != &c->Base.Program.Instructions;
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inst = inst->Next) {
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const struct rc_opcode_info * opcode;
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struct rc_sub_instruction copy;
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if (inst->Type != RC_INSTRUCTION_NORMAL)
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continue;
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opcode = rc_get_opcode_info(inst->U.I.Opcode);
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if (opcode->HasTexture || opcode->IsFlowControl || opcode->Opcode == RC_OPCODE_KIL)
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continue;
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copy = inst->U.I;
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check_opcode_support(c, ©);
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final_rewrite(©);
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inst->Type = RC_INSTRUCTION_PAIR;
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set_pair_instruction(c, &inst->U.P, ©);
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}
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}
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