/*
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* Copyright 2011 Christoph Bumiller
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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#ifndef __NV50_IR_DRIVER_H__
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#define __NV50_IR_DRIVER_H__
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#include "pipe/p_shader_tokens.h"
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#include "tgsi/tgsi_util.h"
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#include "tgsi/tgsi_parse.h"
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#include "tgsi/tgsi_scan.h"
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/*
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* This struct constitutes linkage information in TGSI terminology.
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*
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* It is created by the code generator and handed to the pipe driver
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* for input/output slot assignment.
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*/
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struct nv50_ir_varying
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{
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uint8_t slot[4]; /* native slots for xyzw (addresses in 32-bit words) */
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unsigned mask : 4; /* vec4 mask */
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unsigned linear : 1; /* linearly interpolated if true (and not flat) */
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unsigned flat : 1;
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unsigned sc : 1; /* special colour interpolation mode (SHADE_MODEL) */
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unsigned centroid : 1;
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unsigned patch : 1; /* patch constant value */
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unsigned regular : 1; /* driver-specific meaning (e.g. input in sreg) */
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unsigned input : 1; /* indicates direction of system values */
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unsigned oread : 1; /* true if output is read from parallel TCP */
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ubyte id; /* TGSI register index */
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ubyte sn; /* TGSI semantic name */
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ubyte si; /* TGSI semantic index */
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};
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#ifdef DEBUG
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# define NV50_IR_DEBUG_BASIC (1 << 0)
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# define NV50_IR_DEBUG_VERBOSE (2 << 0)
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# define NV50_IR_DEBUG_REG_ALLOC (1 << 2)
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#else
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# define NV50_IR_DEBUG_BASIC 0
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# define NV50_IR_DEBUG_VERBOSE 0
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# define NV50_IR_DEBUG_REG_ALLOC 0
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#endif
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struct nv50_ir_prog_symbol
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{
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uint32_t label;
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uint32_t offset;
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};
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#define NVISA_GK104_CHIPSET 0xe0
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#define NVISA_GK20A_CHIPSET 0xea
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#define NVISA_GM107_CHIPSET 0x110
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struct nv50_ir_prog_info
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{
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uint16_t target; /* chipset (0x50, 0x84, 0xc0, ...) */
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uint8_t type; /* PIPE_SHADER */
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uint8_t optLevel; /* optimization level (0 to 3) */
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uint8_t dbgFlags;
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bool omitLineNum; /* only used for printing the prog when dbgFlags is set */
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struct {
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int16_t maxGPR; /* may be -1 if none used */
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int16_t maxOutput;
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uint32_t tlsSpace; /* required local memory per thread */
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uint32_t smemSize; /* required shared memory per block */
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uint32_t *code;
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uint32_t codeSize;
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uint32_t instructions;
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uint8_t sourceRep; /* PIPE_SHADER_IR_* */
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const void *source;
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void *relocData;
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void *fixupData;
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struct nv50_ir_prog_symbol *syms;
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uint16_t numSyms;
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} bin;
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struct nv50_ir_varying sv[PIPE_MAX_SHADER_INPUTS];
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struct nv50_ir_varying in[PIPE_MAX_SHADER_INPUTS];
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struct nv50_ir_varying out[PIPE_MAX_SHADER_OUTPUTS];
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uint8_t numInputs;
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uint8_t numOutputs;
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uint8_t numPatchConstants; /* also included in numInputs/numOutputs */
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uint8_t numSysVals;
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struct {
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uint32_t *buf; /* for IMMEDIATE_ARRAY */
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uint16_t bufSize; /* size of immediate array */
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uint16_t count; /* count of inline immediates */
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uint32_t *data; /* inline immediate data */
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uint8_t *type; /* for each vec4 (128 bit) */
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} immd;
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union {
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struct {
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uint32_t inputMask[4]; /* mask of attributes read (1 bit per scalar) */
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bool usesDrawParameters;
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} vp;
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struct {
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uint8_t inputPatchSize;
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uint8_t outputPatchSize;
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uint8_t partitioning; /* PIPE_TESS_PART */
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int8_t winding; /* +1 (clockwise) / -1 (counter-clockwise) */
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uint8_t domain; /* PIPE_PRIM_{QUADS,TRIANGLES,LINES} */
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uint8_t outputPrim; /* PIPE_PRIM_{TRIANGLES,LINES,POINTS} */
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} tp;
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struct {
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uint8_t inputPrim;
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uint8_t outputPrim;
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unsigned instanceCount;
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unsigned maxVertices;
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} gp;
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struct {
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unsigned numColourResults;
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bool writesDepth;
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bool earlyFragTests;
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bool postDepthCoverage;
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bool separateFragData;
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bool usesDiscard;
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bool persampleInvocation;
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bool usesSampleMaskIn;
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bool readsFramebuffer;
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} fp;
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struct {
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uint32_t inputOffset; /* base address for user args */
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uint32_t sharedOffset; /* reserved space in s[] */
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uint32_t gridInfoBase; /* base address for NTID,NCTAID */
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uint16_t numThreads[3]; /* max number of threads */
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} cp;
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} prop;
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uint8_t numBarriers;
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struct {
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uint8_t clipDistances; /* number of clip distance outputs */
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uint8_t cullDistances; /* number of cull distance outputs */
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int8_t genUserClip; /* request user clip planes for ClipVertex */
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uint8_t auxCBSlot; /* driver constant buffer slot */
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uint16_t ucpBase; /* base address for UCPs */
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uint16_t drawInfoBase; /* base address for draw parameters */
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uint16_t alphaRefBase; /* base address for alpha test values */
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uint8_t pointSize; /* output index for PointSize */
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uint8_t instanceId; /* system value index of InstanceID */
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uint8_t vertexId; /* system value index of VertexID */
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uint8_t edgeFlagIn;
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uint8_t edgeFlagOut;
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int8_t viewportId; /* output index of ViewportIndex */
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uint8_t fragDepth; /* output index of FragDepth */
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uint8_t sampleMask; /* output index of SampleMask */
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uint8_t backFaceColor[2]; /* input/output indices of back face colour */
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uint8_t globalAccess; /* 1 for read, 2 for wr, 3 for rw */
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bool fp64; /* program uses fp64 math */
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bool mul_zero_wins; /* program wants for x*0 = 0 */
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bool nv50styleSurfaces; /* generate gX[] access for raw buffers */
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uint16_t texBindBase; /* base address for tex handles (nve4) */
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uint16_t fbtexBindBase; /* base address for fbtex handle (nve4) */
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uint16_t suInfoBase; /* base address for surface info (nve4) */
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uint16_t bindlessBase; /* base address for bindless image info (nve4) */
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uint16_t bufInfoBase; /* base address for buffer info */
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uint16_t sampleInfoBase; /* base address for sample positions */
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uint8_t msInfoCBSlot; /* cX[] used for multisample info */
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uint16_t msInfoBase; /* base address for multisample info */
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uint16_t uboInfoBase; /* base address for compute UBOs (gk104+) */
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} io;
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/* driver callback to assign input/output locations */
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int (*assignSlots)(struct nv50_ir_prog_info *);
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void *driverPriv;
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};
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#ifdef __cplusplus
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extern "C" {
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#endif
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extern int nv50_ir_generate_code(struct nv50_ir_prog_info *);
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extern void nv50_ir_relocate_code(void *relocData, uint32_t *code,
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uint32_t codePos,
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uint32_t libPos,
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uint32_t dataPos);
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extern void
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nv50_ir_apply_fixups(void *fixupData, uint32_t *code,
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bool force_per_sample, bool flatshade,
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uint8_t alphatest);
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/* obtain code that will be shared among programs */
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extern void nv50_ir_get_target_library(uint32_t chipset,
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const uint32_t **code, uint32_t *size);
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#ifdef __cplusplus
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}
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#endif
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#endif // __NV50_IR_DRIVER_H__
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