/*
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* Copyright (C) 2014 The Android Open Source Project
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#ifndef ART_COMPILER_OPTIMIZING_CODE_GENERATOR_ARM64_H_
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#define ART_COMPILER_OPTIMIZING_CODE_GENERATOR_ARM64_H_
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#include "base/bit_field.h"
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#include "code_generator.h"
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#include "common_arm64.h"
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#include "dex/dex_file_types.h"
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#include "dex/string_reference.h"
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#include "dex/type_reference.h"
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#include "driver/compiler_options.h"
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#include "nodes.h"
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#include "parallel_move_resolver.h"
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#include "utils/arm64/assembler_arm64.h"
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// TODO(VIXL): Make VIXL compile with -Wshadow.
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#pragma GCC diagnostic push
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#pragma GCC diagnostic ignored "-Wshadow"
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#include "aarch64/disasm-aarch64.h"
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#include "aarch64/macro-assembler-aarch64.h"
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#pragma GCC diagnostic pop
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namespace art {
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namespace linker {
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class Arm64RelativePatcherTest;
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} // namespace linker
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namespace arm64 {
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class CodeGeneratorARM64;
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// Use a local definition to prevent copying mistakes.
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static constexpr size_t kArm64WordSize = static_cast<size_t>(kArm64PointerSize);
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// These constants are used as an approximate margin when emission of veneer and literal pools
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// must be blocked.
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static constexpr int kMaxMacroInstructionSizeInBytes = 15 * vixl::aarch64::kInstructionSize;
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static constexpr int kInvokeCodeMarginSizeInBytes = 6 * kMaxMacroInstructionSizeInBytes;
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static const vixl::aarch64::Register kParameterCoreRegisters[] = {
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vixl::aarch64::x1,
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vixl::aarch64::x2,
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vixl::aarch64::x3,
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vixl::aarch64::x4,
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vixl::aarch64::x5,
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vixl::aarch64::x6,
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vixl::aarch64::x7
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};
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static constexpr size_t kParameterCoreRegistersLength = arraysize(kParameterCoreRegisters);
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static const vixl::aarch64::FPRegister kParameterFPRegisters[] = {
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vixl::aarch64::d0,
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vixl::aarch64::d1,
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vixl::aarch64::d2,
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vixl::aarch64::d3,
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vixl::aarch64::d4,
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vixl::aarch64::d5,
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vixl::aarch64::d6,
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vixl::aarch64::d7
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};
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static constexpr size_t kParameterFPRegistersLength = arraysize(kParameterFPRegisters);
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// Thread Register.
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const vixl::aarch64::Register tr = vixl::aarch64::x19;
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// Marking Register.
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const vixl::aarch64::Register mr = vixl::aarch64::x20;
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// Method register on invoke.
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static const vixl::aarch64::Register kArtMethodRegister = vixl::aarch64::x0;
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const vixl::aarch64::CPURegList vixl_reserved_core_registers(vixl::aarch64::ip0,
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vixl::aarch64::ip1);
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const vixl::aarch64::CPURegList vixl_reserved_fp_registers(vixl::aarch64::d31);
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const vixl::aarch64::CPURegList runtime_reserved_core_registers =
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vixl::aarch64::CPURegList(
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tr,
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// Reserve X20 as Marking Register when emitting Baker read barriers.
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((kEmitCompilerReadBarrier && kUseBakerReadBarrier) ? mr : vixl::aarch64::NoCPUReg),
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vixl::aarch64::lr);
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// Some instructions have special requirements for a temporary, for example
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// LoadClass/kBssEntry and LoadString/kBssEntry for Baker read barrier require
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// temp that's not an R0 (to avoid an extra move) and Baker read barrier field
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// loads with large offsets need a fixed register to limit the number of link-time
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// thunks we generate. For these and similar cases, we want to reserve a specific
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// register that's neither callee-save nor an argument register. We choose x15.
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inline Location FixedTempLocation() {
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return Location::RegisterLocation(vixl::aarch64::x15.GetCode());
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}
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// Callee-save registers AAPCS64, without x19 (Thread Register) (nor
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// x20 (Marking Register) when emitting Baker read barriers).
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const vixl::aarch64::CPURegList callee_saved_core_registers(
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vixl::aarch64::CPURegister::kRegister,
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vixl::aarch64::kXRegSize,
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((kEmitCompilerReadBarrier && kUseBakerReadBarrier)
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? vixl::aarch64::x21.GetCode()
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: vixl::aarch64::x20.GetCode()),
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vixl::aarch64::x30.GetCode());
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const vixl::aarch64::CPURegList callee_saved_fp_registers(vixl::aarch64::CPURegister::kFPRegister,
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vixl::aarch64::kDRegSize,
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vixl::aarch64::d8.GetCode(),
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vixl::aarch64::d15.GetCode());
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Location ARM64ReturnLocation(DataType::Type return_type);
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class SlowPathCodeARM64 : public SlowPathCode {
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public:
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explicit SlowPathCodeARM64(HInstruction* instruction)
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: SlowPathCode(instruction), entry_label_(), exit_label_() {}
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vixl::aarch64::Label* GetEntryLabel() { return &entry_label_; }
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vixl::aarch64::Label* GetExitLabel() { return &exit_label_; }
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void SaveLiveRegisters(CodeGenerator* codegen, LocationSummary* locations) override;
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void RestoreLiveRegisters(CodeGenerator* codegen, LocationSummary* locations) override;
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private:
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vixl::aarch64::Label entry_label_;
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vixl::aarch64::Label exit_label_;
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DISALLOW_COPY_AND_ASSIGN(SlowPathCodeARM64);
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};
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class JumpTableARM64 : public DeletableArenaObject<kArenaAllocSwitchTable> {
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public:
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explicit JumpTableARM64(HPackedSwitch* switch_instr)
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: switch_instr_(switch_instr), table_start_() {}
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vixl::aarch64::Label* GetTableStartLabel() { return &table_start_; }
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void EmitTable(CodeGeneratorARM64* codegen);
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private:
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HPackedSwitch* const switch_instr_;
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vixl::aarch64::Label table_start_;
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DISALLOW_COPY_AND_ASSIGN(JumpTableARM64);
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};
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static const vixl::aarch64::Register kRuntimeParameterCoreRegisters[] =
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{ vixl::aarch64::x0,
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vixl::aarch64::x1,
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vixl::aarch64::x2,
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vixl::aarch64::x3,
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vixl::aarch64::x4,
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vixl::aarch64::x5,
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vixl::aarch64::x6,
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vixl::aarch64::x7 };
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static constexpr size_t kRuntimeParameterCoreRegistersLength =
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arraysize(kRuntimeParameterCoreRegisters);
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static const vixl::aarch64::FPRegister kRuntimeParameterFpuRegisters[] =
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{ vixl::aarch64::d0,
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vixl::aarch64::d1,
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vixl::aarch64::d2,
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vixl::aarch64::d3,
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vixl::aarch64::d4,
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vixl::aarch64::d5,
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vixl::aarch64::d6,
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vixl::aarch64::d7 };
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static constexpr size_t kRuntimeParameterFpuRegistersLength =
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arraysize(kRuntimeParameterCoreRegisters);
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class InvokeRuntimeCallingConvention : public CallingConvention<vixl::aarch64::Register,
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vixl::aarch64::FPRegister> {
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public:
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static constexpr size_t kParameterCoreRegistersLength = arraysize(kParameterCoreRegisters);
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InvokeRuntimeCallingConvention()
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: CallingConvention(kRuntimeParameterCoreRegisters,
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kRuntimeParameterCoreRegistersLength,
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kRuntimeParameterFpuRegisters,
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kRuntimeParameterFpuRegistersLength,
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kArm64PointerSize) {}
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Location GetReturnLocation(DataType::Type return_type);
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private:
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DISALLOW_COPY_AND_ASSIGN(InvokeRuntimeCallingConvention);
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};
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class InvokeDexCallingConvention : public CallingConvention<vixl::aarch64::Register,
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vixl::aarch64::FPRegister> {
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public:
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InvokeDexCallingConvention()
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: CallingConvention(kParameterCoreRegisters,
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kParameterCoreRegistersLength,
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kParameterFPRegisters,
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kParameterFPRegistersLength,
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kArm64PointerSize) {}
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Location GetReturnLocation(DataType::Type return_type) const {
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return ARM64ReturnLocation(return_type);
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}
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private:
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DISALLOW_COPY_AND_ASSIGN(InvokeDexCallingConvention);
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};
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class InvokeDexCallingConventionVisitorARM64 : public InvokeDexCallingConventionVisitor {
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public:
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InvokeDexCallingConventionVisitorARM64() {}
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virtual ~InvokeDexCallingConventionVisitorARM64() {}
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Location GetNextLocation(DataType::Type type) override;
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Location GetReturnLocation(DataType::Type return_type) const override {
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return calling_convention.GetReturnLocation(return_type);
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}
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Location GetMethodLocation() const override;
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private:
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InvokeDexCallingConvention calling_convention;
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DISALLOW_COPY_AND_ASSIGN(InvokeDexCallingConventionVisitorARM64);
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};
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class FieldAccessCallingConventionARM64 : public FieldAccessCallingConvention {
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public:
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FieldAccessCallingConventionARM64() {}
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Location GetObjectLocation() const override {
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return helpers::LocationFrom(vixl::aarch64::x1);
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}
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Location GetFieldIndexLocation() const override {
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return helpers::LocationFrom(vixl::aarch64::x0);
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}
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Location GetReturnLocation(DataType::Type type ATTRIBUTE_UNUSED) const override {
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return helpers::LocationFrom(vixl::aarch64::x0);
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}
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Location GetSetValueLocation(DataType::Type type ATTRIBUTE_UNUSED,
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bool is_instance) const override {
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return is_instance
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? helpers::LocationFrom(vixl::aarch64::x2)
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: helpers::LocationFrom(vixl::aarch64::x1);
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}
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Location GetFpuLocation(DataType::Type type ATTRIBUTE_UNUSED) const override {
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return helpers::LocationFrom(vixl::aarch64::d0);
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}
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private:
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DISALLOW_COPY_AND_ASSIGN(FieldAccessCallingConventionARM64);
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};
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class InstructionCodeGeneratorARM64 : public InstructionCodeGenerator {
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public:
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InstructionCodeGeneratorARM64(HGraph* graph, CodeGeneratorARM64* codegen);
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#define DECLARE_VISIT_INSTRUCTION(name, super) \
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void Visit##name(H##name* instr) override;
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FOR_EACH_CONCRETE_INSTRUCTION_COMMON(DECLARE_VISIT_INSTRUCTION)
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FOR_EACH_CONCRETE_INSTRUCTION_ARM64(DECLARE_VISIT_INSTRUCTION)
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FOR_EACH_CONCRETE_INSTRUCTION_SHARED(DECLARE_VISIT_INSTRUCTION)
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#undef DECLARE_VISIT_INSTRUCTION
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void VisitInstruction(HInstruction* instruction) override {
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LOG(FATAL) << "Unreachable instruction " << instruction->DebugName()
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<< " (id " << instruction->GetId() << ")";
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}
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Arm64Assembler* GetAssembler() const { return assembler_; }
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vixl::aarch64::MacroAssembler* GetVIXLAssembler() { return GetAssembler()->GetVIXLAssembler(); }
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private:
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void GenerateClassInitializationCheck(SlowPathCodeARM64* slow_path,
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vixl::aarch64::Register class_reg);
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void GenerateBitstringTypeCheckCompare(HTypeCheckInstruction* check,
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vixl::aarch64::Register temp);
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void GenerateSuspendCheck(HSuspendCheck* instruction, HBasicBlock* successor);
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void HandleBinaryOp(HBinaryOperation* instr);
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void HandleFieldSet(HInstruction* instruction,
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const FieldInfo& field_info,
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bool value_can_be_null);
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void HandleFieldGet(HInstruction* instruction, const FieldInfo& field_info);
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void HandleCondition(HCondition* instruction);
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// Generate a heap reference load using one register `out`:
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//
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// out <- *(out + offset)
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//
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// while honoring heap poisoning and/or read barriers (if any).
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//
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// Location `maybe_temp` is used when generating a read barrier and
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// shall be a register in that case; it may be an invalid location
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// otherwise.
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void GenerateReferenceLoadOneRegister(HInstruction* instruction,
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Location out,
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uint32_t offset,
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Location maybe_temp,
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ReadBarrierOption read_barrier_option);
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// Generate a heap reference load using two different registers
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// `out` and `obj`:
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//
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// out <- *(obj + offset)
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//
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// while honoring heap poisoning and/or read barriers (if any).
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//
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// Location `maybe_temp` is used when generating a Baker's (fast
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// path) read barrier and shall be a register in that case; it may
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// be an invalid location otherwise.
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void GenerateReferenceLoadTwoRegisters(HInstruction* instruction,
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Location out,
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Location obj,
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uint32_t offset,
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Location maybe_temp,
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ReadBarrierOption read_barrier_option);
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// Generate a floating-point comparison.
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void GenerateFcmp(HInstruction* instruction);
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void HandleShift(HBinaryOperation* instr);
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void GenerateTestAndBranch(HInstruction* instruction,
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size_t condition_input_index,
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vixl::aarch64::Label* true_target,
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vixl::aarch64::Label* false_target);
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void DivRemOneOrMinusOne(HBinaryOperation* instruction);
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void DivRemByPowerOfTwo(HBinaryOperation* instruction);
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void GenerateDivRemWithAnyConstant(HBinaryOperation* instruction);
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void GenerateIntDiv(HDiv* instruction);
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void GenerateIntDivForConstDenom(HDiv *instruction);
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void GenerateIntDivForPower2Denom(HDiv *instruction);
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void GenerateIntRem(HRem* instruction);
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void GenerateIntRemForConstDenom(HRem *instruction);
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void GenerateIntRemForPower2Denom(HRem *instruction);
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void HandleGoto(HInstruction* got, HBasicBlock* successor);
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vixl::aarch64::MemOperand VecAddress(
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HVecMemoryOperation* instruction,
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// This function may acquire a scratch register.
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vixl::aarch64::UseScratchRegisterScope* temps_scope,
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size_t size,
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bool is_string_char_at,
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/*out*/ vixl::aarch64::Register* scratch);
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Arm64Assembler* const assembler_;
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CodeGeneratorARM64* const codegen_;
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DISALLOW_COPY_AND_ASSIGN(InstructionCodeGeneratorARM64);
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};
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class LocationsBuilderARM64 : public HGraphVisitor {
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public:
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LocationsBuilderARM64(HGraph* graph, CodeGeneratorARM64* codegen)
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: HGraphVisitor(graph), codegen_(codegen) {}
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#define DECLARE_VISIT_INSTRUCTION(name, super) \
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void Visit##name(H##name* instr) override;
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FOR_EACH_CONCRETE_INSTRUCTION_COMMON(DECLARE_VISIT_INSTRUCTION)
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FOR_EACH_CONCRETE_INSTRUCTION_ARM64(DECLARE_VISIT_INSTRUCTION)
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FOR_EACH_CONCRETE_INSTRUCTION_SHARED(DECLARE_VISIT_INSTRUCTION)
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#undef DECLARE_VISIT_INSTRUCTION
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void VisitInstruction(HInstruction* instruction) override {
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LOG(FATAL) << "Unreachable instruction " << instruction->DebugName()
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<< " (id " << instruction->GetId() << ")";
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}
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private:
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void HandleBinaryOp(HBinaryOperation* instr);
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void HandleFieldSet(HInstruction* instruction);
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void HandleFieldGet(HInstruction* instruction, const FieldInfo& field_info);
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void HandleInvoke(HInvoke* instr);
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void HandleCondition(HCondition* instruction);
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void HandleShift(HBinaryOperation* instr);
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CodeGeneratorARM64* const codegen_;
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InvokeDexCallingConventionVisitorARM64 parameter_visitor_;
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DISALLOW_COPY_AND_ASSIGN(LocationsBuilderARM64);
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};
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class ParallelMoveResolverARM64 : public ParallelMoveResolverNoSwap {
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public:
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ParallelMoveResolverARM64(ArenaAllocator* allocator, CodeGeneratorARM64* codegen)
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: ParallelMoveResolverNoSwap(allocator), codegen_(codegen), vixl_temps_() {}
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protected:
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void PrepareForEmitNativeCode() override;
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void FinishEmitNativeCode() override;
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Location AllocateScratchLocationFor(Location::Kind kind) override;
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void FreeScratchLocation(Location loc) override;
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void EmitMove(size_t index) override;
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private:
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Arm64Assembler* GetAssembler() const;
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vixl::aarch64::MacroAssembler* GetVIXLAssembler() const {
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return GetAssembler()->GetVIXLAssembler();
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}
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CodeGeneratorARM64* const codegen_;
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vixl::aarch64::UseScratchRegisterScope vixl_temps_;
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DISALLOW_COPY_AND_ASSIGN(ParallelMoveResolverARM64);
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};
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class CodeGeneratorARM64 : public CodeGenerator {
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public:
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CodeGeneratorARM64(HGraph* graph,
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const CompilerOptions& compiler_options,
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OptimizingCompilerStats* stats = nullptr);
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virtual ~CodeGeneratorARM64() {}
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void GenerateFrameEntry() override;
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void GenerateFrameExit() override;
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vixl::aarch64::CPURegList GetFramePreservedCoreRegisters() const;
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vixl::aarch64::CPURegList GetFramePreservedFPRegisters() const;
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void Bind(HBasicBlock* block) override;
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vixl::aarch64::Label* GetLabelOf(HBasicBlock* block) {
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block = FirstNonEmptyBlock(block);
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return &(block_labels_[block->GetBlockId()]);
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}
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size_t GetWordSize() const override {
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return kArm64WordSize;
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}
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size_t GetFloatingPointSpillSlotSize() const override {
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return GetGraph()->HasSIMD()
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? 2 * kArm64WordSize // 16 bytes == 2 arm64 words for each spill
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: 1 * kArm64WordSize; // 8 bytes == 1 arm64 words for each spill
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}
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uintptr_t GetAddressOf(HBasicBlock* block) override {
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vixl::aarch64::Label* block_entry_label = GetLabelOf(block);
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DCHECK(block_entry_label->IsBound());
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return block_entry_label->GetLocation();
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}
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HGraphVisitor* GetLocationBuilder() override { return &location_builder_; }
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HGraphVisitor* GetInstructionVisitor() override { return &instruction_visitor_; }
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Arm64Assembler* GetAssembler() override { return &assembler_; }
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const Arm64Assembler& GetAssembler() const override { return assembler_; }
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vixl::aarch64::MacroAssembler* GetVIXLAssembler() { return GetAssembler()->GetVIXLAssembler(); }
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// Emit a write barrier.
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void MarkGCCard(vixl::aarch64::Register object,
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vixl::aarch64::Register value,
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bool value_can_be_null);
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void GenerateMemoryBarrier(MemBarrierKind kind);
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// Register allocation.
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void SetupBlockedRegisters() const override;
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size_t SaveCoreRegister(size_t stack_index, uint32_t reg_id) override;
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size_t RestoreCoreRegister(size_t stack_index, uint32_t reg_id) override;
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size_t SaveFloatingPointRegister(size_t stack_index, uint32_t reg_id) override;
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size_t RestoreFloatingPointRegister(size_t stack_index, uint32_t reg_id) override;
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// The number of registers that can be allocated. The register allocator may
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// decide to reserve and not use a few of them.
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// We do not consider registers sp, xzr, wzr. They are either not allocatable
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// (xzr, wzr), or make for poor allocatable registers (sp alignment
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// requirements, etc.). This also facilitates our task as all other registers
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// can easily be mapped via to or from their type and index or code.
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static const int kNumberOfAllocatableRegisters = vixl::aarch64::kNumberOfRegisters - 1;
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static const int kNumberOfAllocatableFPRegisters = vixl::aarch64::kNumberOfFPRegisters;
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static constexpr int kNumberOfAllocatableRegisterPairs = 0;
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void DumpCoreRegister(std::ostream& stream, int reg) const override;
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void DumpFloatingPointRegister(std::ostream& stream, int reg) const override;
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InstructionSet GetInstructionSet() const override {
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return InstructionSet::kArm64;
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}
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const Arm64InstructionSetFeatures& GetInstructionSetFeatures() const;
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void Initialize() override {
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block_labels_.resize(GetGraph()->GetBlocks().size());
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}
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// We want to use the STP and LDP instructions to spill and restore registers for slow paths.
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// These instructions can only encode offsets that are multiples of the register size accessed.
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uint32_t GetPreferredSlotsAlignment() const override { return vixl::aarch64::kXRegSizeInBytes; }
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JumpTableARM64* CreateJumpTable(HPackedSwitch* switch_instr) {
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jump_tables_.emplace_back(new (GetGraph()->GetAllocator()) JumpTableARM64(switch_instr));
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return jump_tables_.back().get();
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}
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void Finalize(CodeAllocator* allocator) override;
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// Code generation helpers.
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void MoveConstant(vixl::aarch64::CPURegister destination, HConstant* constant);
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void MoveConstant(Location destination, int32_t value) override;
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void MoveLocation(Location dst, Location src, DataType::Type dst_type) override;
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void AddLocationAsTemp(Location location, LocationSummary* locations) override;
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void Load(DataType::Type type,
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vixl::aarch64::CPURegister dst,
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const vixl::aarch64::MemOperand& src);
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void Store(DataType::Type type,
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vixl::aarch64::CPURegister src,
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const vixl::aarch64::MemOperand& dst);
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void LoadAcquire(HInstruction* instruction,
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vixl::aarch64::CPURegister dst,
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const vixl::aarch64::MemOperand& src,
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bool needs_null_check);
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void StoreRelease(HInstruction* instruction,
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DataType::Type type,
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vixl::aarch64::CPURegister src,
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const vixl::aarch64::MemOperand& dst,
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bool needs_null_check);
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// Generate code to invoke a runtime entry point.
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void InvokeRuntime(QuickEntrypointEnum entrypoint,
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HInstruction* instruction,
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uint32_t dex_pc,
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SlowPathCode* slow_path = nullptr) override;
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// Generate code to invoke a runtime entry point, but do not record
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// PC-related information in a stack map.
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void InvokeRuntimeWithoutRecordingPcInfo(int32_t entry_point_offset,
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HInstruction* instruction,
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SlowPathCode* slow_path);
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ParallelMoveResolverARM64* GetMoveResolver() override { return &move_resolver_; }
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bool NeedsTwoRegisters(DataType::Type type ATTRIBUTE_UNUSED) const override {
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return false;
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}
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// Check if the desired_string_load_kind is supported. If it is, return it,
|
// otherwise return a fall-back kind that should be used instead.
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HLoadString::LoadKind GetSupportedLoadStringKind(
|
HLoadString::LoadKind desired_string_load_kind) override;
|
|
// Check if the desired_class_load_kind is supported. If it is, return it,
|
// otherwise return a fall-back kind that should be used instead.
|
HLoadClass::LoadKind GetSupportedLoadClassKind(
|
HLoadClass::LoadKind desired_class_load_kind) override;
|
|
// Check if the desired_dispatch_info is supported. If it is, return it,
|
// otherwise return a fall-back info that should be used instead.
|
HInvokeStaticOrDirect::DispatchInfo GetSupportedInvokeStaticOrDirectDispatch(
|
const HInvokeStaticOrDirect::DispatchInfo& desired_dispatch_info,
|
ArtMethod* method) override;
|
|
void GenerateStaticOrDirectCall(
|
HInvokeStaticOrDirect* invoke, Location temp, SlowPathCode* slow_path = nullptr) override;
|
void GenerateVirtualCall(
|
HInvokeVirtual* invoke, Location temp, SlowPathCode* slow_path = nullptr) override;
|
|
void MoveFromReturnRegister(Location trg ATTRIBUTE_UNUSED,
|
DataType::Type type ATTRIBUTE_UNUSED) override {
|
UNIMPLEMENTED(FATAL);
|
}
|
|
// Add a new boot image intrinsic patch for an instruction and return the label
|
// to be bound before the instruction. The instruction will be either the
|
// ADRP (pass `adrp_label = null`) or the ADD (pass `adrp_label` pointing
|
// to the associated ADRP patch label).
|
vixl::aarch64::Label* NewBootImageIntrinsicPatch(uint32_t intrinsic_data,
|
vixl::aarch64::Label* adrp_label = nullptr);
|
|
// Add a new boot image relocation patch for an instruction and return the label
|
// to be bound before the instruction. The instruction will be either the
|
// ADRP (pass `adrp_label = null`) or the LDR (pass `adrp_label` pointing
|
// to the associated ADRP patch label).
|
vixl::aarch64::Label* NewBootImageRelRoPatch(uint32_t boot_image_offset,
|
vixl::aarch64::Label* adrp_label = nullptr);
|
|
// Add a new boot image method patch for an instruction and return the label
|
// to be bound before the instruction. The instruction will be either the
|
// ADRP (pass `adrp_label = null`) or the ADD (pass `adrp_label` pointing
|
// to the associated ADRP patch label).
|
vixl::aarch64::Label* NewBootImageMethodPatch(MethodReference target_method,
|
vixl::aarch64::Label* adrp_label = nullptr);
|
|
// Add a new .bss entry method patch for an instruction and return
|
// the label to be bound before the instruction. The instruction will be
|
// either the ADRP (pass `adrp_label = null`) or the LDR (pass `adrp_label`
|
// pointing to the associated ADRP patch label).
|
vixl::aarch64::Label* NewMethodBssEntryPatch(MethodReference target_method,
|
vixl::aarch64::Label* adrp_label = nullptr);
|
|
// Add a new boot image type patch for an instruction and return the label
|
// to be bound before the instruction. The instruction will be either the
|
// ADRP (pass `adrp_label = null`) or the ADD (pass `adrp_label` pointing
|
// to the associated ADRP patch label).
|
vixl::aarch64::Label* NewBootImageTypePatch(const DexFile& dex_file,
|
dex::TypeIndex type_index,
|
vixl::aarch64::Label* adrp_label = nullptr);
|
|
// Add a new .bss entry type patch for an instruction and return the label
|
// to be bound before the instruction. The instruction will be either the
|
// ADRP (pass `adrp_label = null`) or the ADD (pass `adrp_label` pointing
|
// to the associated ADRP patch label).
|
vixl::aarch64::Label* NewBssEntryTypePatch(const DexFile& dex_file,
|
dex::TypeIndex type_index,
|
vixl::aarch64::Label* adrp_label = nullptr);
|
|
// Add a new boot image string patch for an instruction and return the label
|
// to be bound before the instruction. The instruction will be either the
|
// ADRP (pass `adrp_label = null`) or the ADD (pass `adrp_label` pointing
|
// to the associated ADRP patch label).
|
vixl::aarch64::Label* NewBootImageStringPatch(const DexFile& dex_file,
|
dex::StringIndex string_index,
|
vixl::aarch64::Label* adrp_label = nullptr);
|
|
// Add a new .bss entry string patch for an instruction and return the label
|
// to be bound before the instruction. The instruction will be either the
|
// ADRP (pass `adrp_label = null`) or the ADD (pass `adrp_label` pointing
|
// to the associated ADRP patch label).
|
vixl::aarch64::Label* NewStringBssEntryPatch(const DexFile& dex_file,
|
dex::StringIndex string_index,
|
vixl::aarch64::Label* adrp_label = nullptr);
|
|
// Emit the CBNZ instruction for baker read barrier and record
|
// the associated patch for AOT or slow path for JIT.
|
void EmitBakerReadBarrierCbnz(uint32_t custom_data);
|
|
vixl::aarch64::Literal<uint32_t>* DeduplicateBootImageAddressLiteral(uint64_t address);
|
vixl::aarch64::Literal<uint32_t>* DeduplicateJitStringLiteral(const DexFile& dex_file,
|
dex::StringIndex string_index,
|
Handle<mirror::String> handle);
|
vixl::aarch64::Literal<uint32_t>* DeduplicateJitClassLiteral(const DexFile& dex_file,
|
dex::TypeIndex string_index,
|
Handle<mirror::Class> handle);
|
|
void EmitAdrpPlaceholder(vixl::aarch64::Label* fixup_label, vixl::aarch64::Register reg);
|
void EmitAddPlaceholder(vixl::aarch64::Label* fixup_label,
|
vixl::aarch64::Register out,
|
vixl::aarch64::Register base);
|
void EmitLdrOffsetPlaceholder(vixl::aarch64::Label* fixup_label,
|
vixl::aarch64::Register out,
|
vixl::aarch64::Register base);
|
|
void LoadBootImageAddress(vixl::aarch64::Register reg, uint32_t boot_image_reference);
|
void AllocateInstanceForIntrinsic(HInvokeStaticOrDirect* invoke, uint32_t boot_image_offset);
|
|
void EmitLinkerPatches(ArenaVector<linker::LinkerPatch>* linker_patches) override;
|
bool NeedsThunkCode(const linker::LinkerPatch& patch) const override;
|
void EmitThunkCode(const linker::LinkerPatch& patch,
|
/*out*/ ArenaVector<uint8_t>* code,
|
/*out*/ std::string* debug_name) override;
|
|
void EmitJitRootPatches(uint8_t* code, const uint8_t* roots_data) override;
|
|
// Generate a GC root reference load:
|
//
|
// root <- *(obj + offset)
|
//
|
// while honoring read barriers based on read_barrier_option.
|
void GenerateGcRootFieldLoad(HInstruction* instruction,
|
Location root,
|
vixl::aarch64::Register obj,
|
uint32_t offset,
|
vixl::aarch64::Label* fixup_label,
|
ReadBarrierOption read_barrier_option);
|
// Generate MOV for the `old_value` in UnsafeCASObject and mark it with Baker read barrier.
|
void GenerateUnsafeCasOldValueMovWithBakerReadBarrier(vixl::aarch64::Register marked,
|
vixl::aarch64::Register old_value);
|
// Fast path implementation of ReadBarrier::Barrier for a heap
|
// reference field load when Baker's read barriers are used.
|
// Overload suitable for Unsafe.getObject/-Volatile() intrinsic.
|
void GenerateFieldLoadWithBakerReadBarrier(HInstruction* instruction,
|
Location ref,
|
vixl::aarch64::Register obj,
|
const vixl::aarch64::MemOperand& src,
|
bool needs_null_check,
|
bool use_load_acquire);
|
// Fast path implementation of ReadBarrier::Barrier for a heap
|
// reference field load when Baker's read barriers are used.
|
void GenerateFieldLoadWithBakerReadBarrier(HInstruction* instruction,
|
Location ref,
|
vixl::aarch64::Register obj,
|
uint32_t offset,
|
Location maybe_temp,
|
bool needs_null_check,
|
bool use_load_acquire);
|
// Fast path implementation of ReadBarrier::Barrier for a heap
|
// reference array load when Baker's read barriers are used.
|
void GenerateArrayLoadWithBakerReadBarrier(HArrayGet* instruction,
|
Location ref,
|
vixl::aarch64::Register obj,
|
uint32_t data_offset,
|
Location index,
|
bool needs_null_check);
|
|
// Emit code checking the status of the Marking Register, and
|
// aborting the program if MR does not match the value stored in the
|
// art::Thread object. Code is only emitted in debug mode and if
|
// CompilerOptions::EmitRunTimeChecksInDebugMode returns true.
|
//
|
// Argument `code` is used to identify the different occurrences of
|
// MaybeGenerateMarkingRegisterCheck in the code generator, and is
|
// passed to the BRK instruction.
|
//
|
// If `temp_loc` is a valid location, it is expected to be a
|
// register and will be used as a temporary to generate code;
|
// otherwise, a temporary will be fetched from the core register
|
// scratch pool.
|
virtual void MaybeGenerateMarkingRegisterCheck(int code,
|
Location temp_loc = Location::NoLocation());
|
|
// Generate a read barrier for a heap reference within `instruction`
|
// using a slow path.
|
//
|
// A read barrier for an object reference read from the heap is
|
// implemented as a call to the artReadBarrierSlow runtime entry
|
// point, which is passed the values in locations `ref`, `obj`, and
|
// `offset`:
|
//
|
// mirror::Object* artReadBarrierSlow(mirror::Object* ref,
|
// mirror::Object* obj,
|
// uint32_t offset);
|
//
|
// The `out` location contains the value returned by
|
// artReadBarrierSlow.
|
//
|
// When `index` is provided (i.e. for array accesses), the offset
|
// value passed to artReadBarrierSlow is adjusted to take `index`
|
// into account.
|
void GenerateReadBarrierSlow(HInstruction* instruction,
|
Location out,
|
Location ref,
|
Location obj,
|
uint32_t offset,
|
Location index = Location::NoLocation());
|
|
// If read barriers are enabled, generate a read barrier for a heap
|
// reference using a slow path. If heap poisoning is enabled, also
|
// unpoison the reference in `out`.
|
void MaybeGenerateReadBarrierSlow(HInstruction* instruction,
|
Location out,
|
Location ref,
|
Location obj,
|
uint32_t offset,
|
Location index = Location::NoLocation());
|
|
// Generate a read barrier for a GC root within `instruction` using
|
// a slow path.
|
//
|
// A read barrier for an object reference GC root is implemented as
|
// a call to the artReadBarrierForRootSlow runtime entry point,
|
// which is passed the value in location `root`:
|
//
|
// mirror::Object* artReadBarrierForRootSlow(GcRoot<mirror::Object>* root);
|
//
|
// The `out` location contains the value returned by
|
// artReadBarrierForRootSlow.
|
void GenerateReadBarrierForRootSlow(HInstruction* instruction, Location out, Location root);
|
|
void GenerateNop() override;
|
|
void GenerateImplicitNullCheck(HNullCheck* instruction) override;
|
void GenerateExplicitNullCheck(HNullCheck* instruction) override;
|
|
private:
|
// Encoding of thunk type and data for link-time generated thunks for Baker read barriers.
|
|
enum class BakerReadBarrierKind : uint8_t {
|
kField, // Field get or array get with constant offset (i.e. constant index).
|
kAcquire, // Volatile field get.
|
kArray, // Array get with index in register.
|
kGcRoot, // GC root load.
|
kLast = kGcRoot
|
};
|
|
static constexpr uint32_t kBakerReadBarrierInvalidEncodedReg = /* sp/zr is invalid */ 31u;
|
|
static constexpr size_t kBitsForBakerReadBarrierKind =
|
MinimumBitsToStore(static_cast<size_t>(BakerReadBarrierKind::kLast));
|
static constexpr size_t kBakerReadBarrierBitsForRegister =
|
MinimumBitsToStore(kBakerReadBarrierInvalidEncodedReg);
|
using BakerReadBarrierKindField =
|
BitField<BakerReadBarrierKind, 0, kBitsForBakerReadBarrierKind>;
|
using BakerReadBarrierFirstRegField =
|
BitField<uint32_t, kBitsForBakerReadBarrierKind, kBakerReadBarrierBitsForRegister>;
|
using BakerReadBarrierSecondRegField =
|
BitField<uint32_t,
|
kBitsForBakerReadBarrierKind + kBakerReadBarrierBitsForRegister,
|
kBakerReadBarrierBitsForRegister>;
|
|
static void CheckValidReg(uint32_t reg) {
|
DCHECK(reg < vixl::aarch64::lr.GetCode() &&
|
reg != vixl::aarch64::ip0.GetCode() &&
|
reg != vixl::aarch64::ip1.GetCode()) << reg;
|
}
|
|
static inline uint32_t EncodeBakerReadBarrierFieldData(uint32_t base_reg, uint32_t holder_reg) {
|
CheckValidReg(base_reg);
|
CheckValidReg(holder_reg);
|
return BakerReadBarrierKindField::Encode(BakerReadBarrierKind::kField) |
|
BakerReadBarrierFirstRegField::Encode(base_reg) |
|
BakerReadBarrierSecondRegField::Encode(holder_reg);
|
}
|
|
static inline uint32_t EncodeBakerReadBarrierAcquireData(uint32_t base_reg, uint32_t holder_reg) {
|
CheckValidReg(base_reg);
|
CheckValidReg(holder_reg);
|
DCHECK_NE(base_reg, holder_reg);
|
return BakerReadBarrierKindField::Encode(BakerReadBarrierKind::kAcquire) |
|
BakerReadBarrierFirstRegField::Encode(base_reg) |
|
BakerReadBarrierSecondRegField::Encode(holder_reg);
|
}
|
|
static inline uint32_t EncodeBakerReadBarrierArrayData(uint32_t base_reg) {
|
CheckValidReg(base_reg);
|
return BakerReadBarrierKindField::Encode(BakerReadBarrierKind::kArray) |
|
BakerReadBarrierFirstRegField::Encode(base_reg) |
|
BakerReadBarrierSecondRegField::Encode(kBakerReadBarrierInvalidEncodedReg);
|
}
|
|
static inline uint32_t EncodeBakerReadBarrierGcRootData(uint32_t root_reg) {
|
CheckValidReg(root_reg);
|
return BakerReadBarrierKindField::Encode(BakerReadBarrierKind::kGcRoot) |
|
BakerReadBarrierFirstRegField::Encode(root_reg) |
|
BakerReadBarrierSecondRegField::Encode(kBakerReadBarrierInvalidEncodedReg);
|
}
|
|
void CompileBakerReadBarrierThunk(Arm64Assembler& assembler,
|
uint32_t encoded_data,
|
/*out*/ std::string* debug_name);
|
|
using Uint64ToLiteralMap = ArenaSafeMap<uint64_t, vixl::aarch64::Literal<uint64_t>*>;
|
using Uint32ToLiteralMap = ArenaSafeMap<uint32_t, vixl::aarch64::Literal<uint32_t>*>;
|
using StringToLiteralMap = ArenaSafeMap<StringReference,
|
vixl::aarch64::Literal<uint32_t>*,
|
StringReferenceValueComparator>;
|
using TypeToLiteralMap = ArenaSafeMap<TypeReference,
|
vixl::aarch64::Literal<uint32_t>*,
|
TypeReferenceValueComparator>;
|
|
vixl::aarch64::Literal<uint32_t>* DeduplicateUint32Literal(uint32_t value);
|
vixl::aarch64::Literal<uint64_t>* DeduplicateUint64Literal(uint64_t value);
|
|
// The PcRelativePatchInfo is used for PC-relative addressing of methods/strings/types,
|
// whether through .data.bimg.rel.ro, .bss, or directly in the boot image.
|
struct PcRelativePatchInfo : PatchInfo<vixl::aarch64::Label> {
|
PcRelativePatchInfo(const DexFile* dex_file, uint32_t off_or_idx)
|
: PatchInfo<vixl::aarch64::Label>(dex_file, off_or_idx), pc_insn_label() { }
|
|
vixl::aarch64::Label* pc_insn_label;
|
};
|
|
struct BakerReadBarrierPatchInfo {
|
explicit BakerReadBarrierPatchInfo(uint32_t data) : label(), custom_data(data) { }
|
|
vixl::aarch64::Label label;
|
uint32_t custom_data;
|
};
|
|
vixl::aarch64::Label* NewPcRelativePatch(const DexFile* dex_file,
|
uint32_t offset_or_index,
|
vixl::aarch64::Label* adrp_label,
|
ArenaDeque<PcRelativePatchInfo>* patches);
|
|
void EmitJumpTables();
|
|
template <linker::LinkerPatch (*Factory)(size_t, const DexFile*, uint32_t, uint32_t)>
|
static void EmitPcRelativeLinkerPatches(const ArenaDeque<PcRelativePatchInfo>& infos,
|
ArenaVector<linker::LinkerPatch>* linker_patches);
|
|
// Labels for each block that will be compiled.
|
// We use a deque so that the `vixl::aarch64::Label` objects do not move in memory.
|
ArenaDeque<vixl::aarch64::Label> block_labels_; // Indexed by block id.
|
vixl::aarch64::Label frame_entry_label_;
|
ArenaVector<std::unique_ptr<JumpTableARM64>> jump_tables_;
|
|
LocationsBuilderARM64 location_builder_;
|
InstructionCodeGeneratorARM64 instruction_visitor_;
|
ParallelMoveResolverARM64 move_resolver_;
|
Arm64Assembler assembler_;
|
|
// Deduplication map for 32-bit literals, used for non-patchable boot image addresses.
|
Uint32ToLiteralMap uint32_literals_;
|
// Deduplication map for 64-bit literals, used for non-patchable method address or method code.
|
Uint64ToLiteralMap uint64_literals_;
|
// PC-relative method patch info for kBootImageLinkTimePcRelative/BootImageRelRo.
|
// Also used for type/string patches for kBootImageRelRo (same linker patch as for methods).
|
ArenaDeque<PcRelativePatchInfo> boot_image_method_patches_;
|
// PC-relative method patch info for kBssEntry.
|
ArenaDeque<PcRelativePatchInfo> method_bss_entry_patches_;
|
// PC-relative type patch info for kBootImageLinkTimePcRelative.
|
ArenaDeque<PcRelativePatchInfo> boot_image_type_patches_;
|
// PC-relative type patch info for kBssEntry.
|
ArenaDeque<PcRelativePatchInfo> type_bss_entry_patches_;
|
// PC-relative String patch info for kBootImageLinkTimePcRelative.
|
ArenaDeque<PcRelativePatchInfo> boot_image_string_patches_;
|
// PC-relative String patch info for kBssEntry.
|
ArenaDeque<PcRelativePatchInfo> string_bss_entry_patches_;
|
// PC-relative patch info for IntrinsicObjects.
|
ArenaDeque<PcRelativePatchInfo> boot_image_intrinsic_patches_;
|
// Baker read barrier patch info.
|
ArenaDeque<BakerReadBarrierPatchInfo> baker_read_barrier_patches_;
|
|
// Patches for string literals in JIT compiled code.
|
StringToLiteralMap jit_string_patches_;
|
// Patches for class literals in JIT compiled code.
|
TypeToLiteralMap jit_class_patches_;
|
|
// Baker read barrier slow paths, mapping custom data (uint32_t) to label.
|
// Wrap the label to work around vixl::aarch64::Label being non-copyable
|
// and non-moveable and as such unusable in ArenaSafeMap<>.
|
struct LabelWrapper {
|
LabelWrapper(const LabelWrapper& src)
|
: label() {
|
DCHECK(!src.label.IsLinked() && !src.label.IsBound());
|
}
|
LabelWrapper() = default;
|
vixl::aarch64::Label label;
|
};
|
ArenaSafeMap<uint32_t, LabelWrapper> jit_baker_read_barrier_slow_paths_;
|
|
friend class linker::Arm64RelativePatcherTest;
|
DISALLOW_COPY_AND_ASSIGN(CodeGeneratorARM64);
|
};
|
|
inline Arm64Assembler* ParallelMoveResolverARM64::GetAssembler() const {
|
return codegen_->GetAssembler();
|
}
|
|
} // namespace arm64
|
} // namespace art
|
|
#endif // ART_COMPILER_OPTIMIZING_CODE_GENERATOR_ARM64_H_
|
