/*
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* sv6160_mem_map.h
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* Copyright (C) 2022 cfig <junwei.jiang@seekwavetech.com>
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*
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* Distributed under terms of the MIT license.
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*/
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#ifndef SV6160_MEM_MAP_H
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#define SV6160_MEM_MAP_H
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//#define SKW_MAX_BUF_SIZE 0x400 //1K
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#define SKW_MAX_BUF_SIZE 0x100 //256B
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/*---------------CODE MEM SECTION-------------------------*/
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#define CODE_MEM_BASE_ADDR 0x100000
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#define CODE_MEM_SIZE 0x7A000//488K
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/*-------------------------------------------------------*/
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/*----------------DATA MEM SECTION-----------------------*/
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#define DATA_MEM_BASE_ADDR 0x20200000
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#define DATA_MEM_SIZE 0x40000//256K
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/*-------------------------------------------------------*/
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/*----------------CSCB MEM SECTION-----------------------*/
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#define AHB_REG_BASE_ADDR 0x40000000
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#define AHB_REG_SIZE 0x400
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/*-------------------------------------------------------*/
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/*----------------WREG MEM SECTION-----------------------*/
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#define WREG_MEM_BASE_ADDR 0x40820000
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#define WREG_MEM_SIZE 0xC000//48K
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/*-------------------------------------------------------*/
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/*----------------PHYR MEM SECTION-----------------------*/
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#define PHYR_MEM_BASE_ADDR 0x40830000
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#define PHYR_MEM_SIZE 0x4000//16K
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/*-------------------------------------------------------*/
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/*----------------SMEM MEM SECTION-----------------------*/
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#define SMEM_MEM_BASE_ADDR 0x40A00000
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#define SMEM_MEM_SIZE 0x58000//352K
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/*-------------------------------------------------------*/
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/*----------------UMEM MEM SECTION-----------------------*/
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#define UMEM_MEM_BASE_ADDR 0x401E0000
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#define UMEM_MEM_SIZE 0xC000//48K
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/*-------------------------------------------------------*/
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/*----------------SDIO MEM SECTION-----------------------*/
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#define SDIO_MEM_BASE_ADDR 0x401D0000
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#define SDIO_MEM_SIZE 0x800//2K
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/*-------------------------------------------------------*/
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/*----------------BTDM MEM SECTION-----------------------*/
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#define BTDM_MEM_BASE_ADDR 0x41000000
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#define BTDM_MEM_SIZE 0xC00//3K
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/*-------------------------------------------------------*/
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/*----------------BTBT MEM SECTION-----------------------*/
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#define BTBT_MEM_BASE_ADDR 0x41000400
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#define BTBT_MEM_SIZE 0x400//1K
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/*-------------------------------------------------------*/
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/*----------------BTLE MEM SECTION-----------------------*/
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#define BTLE_MEM_BASE_ADDR 0x41000800
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#define BTLE_MEM_SIZE 0x400//1K
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/*-------------------------------------------------------*/
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/*----------------BTEM MEM SECTION-----------------------*/
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#define BTEM_MEM_BASE_ADDR 0x41010000
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#define BTEM_MEM_SIZE 0xC000//48K
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/*-------------------------------------------------------*/
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/*----------------BTGB MEM SECTION-----------------------*/
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#define BTGB_MEM_BASE_ADDR 0x41022000
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#define BTGB_MEM_SIZE 0x40//64B
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/*-------------------------------------------------------*/
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/*----------------BTRF MEM SECTION-----------------------*/
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#define BTRF_MEM_BASE_ADDR 0x41024000
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#define BTRF_MEM_SIZE 0x510//1K 272B
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/*-------------------------------------------------------*/
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/*----------------BTRF MEM SECTION-----------------------*/
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#define RFTOP_MEM_BASE_ADDR 0x40148000
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#define RFTOP_MEM_SIZE 0xC20//
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/*-------------------------------------------------------*/
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/*----------------BTRF MEM SECTION-----------------------*/
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#define RCLK_MEM_BASE_ADDR 0x40150000
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#define RCLK_MEM_SIZE 0x200//512B
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/*-------------------------------------------------------*/
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/*----------------BTRF MEM SECTION-----------------------*/
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#define BBPLL_MEM_BASE_ADDR 0x40150400
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#define BBPLL_MEM_SIZE 0x200//512B
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/*-------------------------------------------------------*/
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/*-------------------------------------------------------*/
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/*-------------------------------------------------------*/
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#endif /* !SV6160_MEM_MAP_H */
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