/*
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* linux/arch/arm/mach-sunxi/sun8i-cci.c
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*
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* Copyright(c) 2013-2015 Allwinnertech Co., Ltd.
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* http://www.allwinnertech.com
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*
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* Author: sunny <sunny@allwinnertech.com>
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*
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* allwinner sun9i soc platform CCI(Cache Coherent Interconnect) driver.
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* this init version clone from samsung exynos platform.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/errno.h>
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#include <linux/cache.h>
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#include <linux/syscore_ops.h>
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#include <linux/delay.h>
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#include <linux/kernel.h>
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#include <asm/cacheflush.h>
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#include <linux/of_address.h>
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/* Control interface register offsets */
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#define CTLR_OVERRIDE_REG 0x0
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#define SPEC_CTLR_REG 0x4
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#define SECURE_ACCESS_REG 0x8
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#define STATUS_REG 0xc
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#define IMPRECISE_ERR_REG 0x10
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#define PERF_MON_CTRL_REG 0x100
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/* Slave interface */
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#define CCI_C1_SL_IFACE(x) ((x) + 0x5000)
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#define CCI_C0_SL_IFACE(x) ((x) + 0x4000)
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/* Slave interface register */
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#define SNOOP_CTLR_REG 0x0
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/* CORE_MISC SFR */
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#define BACKBONE_SEL_REG 0x0
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#define MDMA_SHARED_CTRL 0x10
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#define SSS_SHARED_CTRL 0x20
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#define G2D_SHARED_CTRL 0x30
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static void __iomem *cci_base;
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static int cci_enabled __read_mostly;
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void enable_cci_snoops(unsigned int cluster_id)
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{
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void __iomem *control_reg;
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unsigned int value;
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if (!cci_enabled)
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return;
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/* pr_info("sunxi cci: enable cluster[%d] snoop\n", cluster_id); */
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if (cluster_id)
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control_reg = CCI_C1_SL_IFACE(cci_base) + SNOOP_CTLR_REG;
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else
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control_reg = CCI_C0_SL_IFACE(cci_base) + SNOOP_CTLR_REG;
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if ((readl(control_reg) & 0x3) == 0x3)
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return;
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/* Turn on CCI snoops */
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value = readl(control_reg);
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value |= 0x3;
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writel(value, control_reg);
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dsb();
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/* Wait for the dust to settle down */
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while (readl(cci_base + STATUS_REG) & 0x1)
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;
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}
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void disable_cci_snoops(unsigned int cluster_id)
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{
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void __iomem *control_reg;
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unsigned int value;
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if (!cci_enabled)
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return;
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if (cluster_id)
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control_reg = CCI_C1_SL_IFACE(cci_base) + SNOOP_CTLR_REG;
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else
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control_reg = CCI_C0_SL_IFACE(cci_base) + SNOOP_CTLR_REG;
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if (!(readl(control_reg) & 0x3))
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return;
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/* Turn off CCI snoops */
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value = readl(control_reg);
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value &= (~0x3);
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writel(value, control_reg);
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dsb();
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/* Wait for the dust to settle down */
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while (readl(cci_base + STATUS_REG) & 0x1)
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;
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}
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/*
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* Use our own MPIDR accessors as the generic ones in asm/cputype.h have
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* __attribute_const__ and we don't want the compiler to assume any
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* constness here.
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*/
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static int read_mpidr(void)
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{
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unsigned int id;
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asm volatile ("mrc\tp15, 0, %0, c0, c0, 5" : "=r" (id));
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return id;
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}
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#if defined(CONFIG_PM)
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static int cci_status[2];
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static int get_cci_snoop_status(unsigned int cluster_id)
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{
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void __iomem *control_reg;
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if (!cci_enabled)
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return 0;
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if (cluster_id)
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control_reg = CCI_C1_SL_IFACE(cci_base) + SNOOP_CTLR_REG;
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else
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control_reg = CCI_C0_SL_IFACE(cci_base) + SNOOP_CTLR_REG;
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if ((readl(control_reg) & 0x3))
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return 1;
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return 0;
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}
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static int cci_suspend(void)
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{
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int i;
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if (!cci_enabled)
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return 0;
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for (i = 0; i < 2; i++)
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cci_status[i] = get_cci_snoop_status(i);
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if (cci_status[0] && (!cci_status[1]))
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disable_cci_snoops(0);
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return 0;
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}
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static void cci_resume(void)
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{
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unsigned int cluster_id = (read_mpidr() >> 8) & 0xf;
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if ((cluster_id != 0) && (cluster_id != 1))
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pr_err("[%s]cluster id error! cluster id %d\n",
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__func__, cluster_id);
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if (cci_enabled) {
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if (cci_status[cluster_id])
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enable_cci_snoops(cluster_id);
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}
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}
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#else
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#define cci_suspend NULL
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#define cci_resume NULL
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#endif
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static struct syscore_ops cci_syscore_ops = {
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.suspend = cci_suspend,
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.resume = cci_resume,
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};
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int __init sun8i_cci_init(void)
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{
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unsigned int cluster_id = (read_mpidr() >> 8) & 0xf;
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struct device_node *np;
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#if defined(CONFIG_SUN8I_CCI)
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cci_enabled = 1;
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#endif
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if (!cci_enabled) {
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pr_info("sunxi cci is not supported\n");
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goto disabled;
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}
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np = of_find_compatible_node(NULL, NULL, "allwinner,sunxi-cci");
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if (!np) {
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pr_err("Can not find sunxi cci device tree\n");
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}
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cci_base = of_iomap(np, 0);
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if (!cci_base) {
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pr_err("cci mem base iomap Failed\n");
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}
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of_node_put(np);
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enable_cci_snoops(cluster_id);
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register_syscore_ops(&cci_syscore_ops);
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disabled:
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return 0;
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}
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