#ifndef CCISS_H
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#define CCISS_H
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#include <linux/genhd.h>
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#include <linux/mutex.h>
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#include "cciss_cmd.h"
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#define NWD_SHIFT 4
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#define MAX_PART (1 << NWD_SHIFT)
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#define IO_OK 0
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#define IO_ERROR 1
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#define IO_NEEDS_RETRY 3
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#define VENDOR_LEN 8
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#define MODEL_LEN 16
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#define REV_LEN 4
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struct ctlr_info;
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typedef struct ctlr_info ctlr_info_t;
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struct access_method {
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void (*submit_command)(ctlr_info_t *h, CommandList_struct *c);
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void (*set_intr_mask)(ctlr_info_t *h, unsigned long val);
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unsigned long (*fifo_full)(ctlr_info_t *h);
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bool (*intr_pending)(ctlr_info_t *h);
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unsigned long (*command_completed)(ctlr_info_t *h);
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};
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typedef struct _drive_info_struct
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{
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unsigned char LunID[8];
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int usage_count;
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struct request_queue *queue;
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sector_t nr_blocks;
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int block_size;
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int heads;
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int sectors;
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int cylinders;
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int raid_level; /* set to -1 to indicate that
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* the drive is not in use/configured
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*/
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int busy_configuring; /* This is set when a drive is being removed
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* to prevent it from being opened or it's
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* queue from being started.
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*/
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struct device dev;
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__u8 serial_no[16]; /* from inquiry page 0x83,
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* not necc. null terminated.
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*/
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char vendor[VENDOR_LEN + 1]; /* SCSI vendor string */
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char model[MODEL_LEN + 1]; /* SCSI model string */
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char rev[REV_LEN + 1]; /* SCSI revision string */
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char device_initialized; /* indicates whether dev is initialized */
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} drive_info_struct;
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struct ctlr_info
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{
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int ctlr;
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char devname[8];
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char *product_name;
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char firm_ver[4]; /* Firmware version */
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struct pci_dev *pdev;
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__u32 board_id;
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void __iomem *vaddr;
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unsigned long paddr;
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int nr_cmds; /* Number of commands allowed on this controller */
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CfgTable_struct __iomem *cfgtable;
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int interrupts_enabled;
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int major;
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int max_commands;
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int commands_outstanding;
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int max_outstanding; /* Debug */
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int num_luns;
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int highest_lun;
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int usage_count; /* number of opens all all minor devices */
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/* Need space for temp sg list
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* number of scatter/gathers supported
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* number of scatter/gathers in chained block
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*/
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struct scatterlist **scatter_list;
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int maxsgentries;
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int chainsize;
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int max_cmd_sgentries;
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SGDescriptor_struct **cmd_sg_list;
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# define PERF_MODE_INT 0
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# define DOORBELL_INT 1
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# define SIMPLE_MODE_INT 2
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# define MEMQ_MODE_INT 3
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unsigned int intr[4];
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unsigned int msix_vector;
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unsigned int msi_vector;
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int intr_mode;
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int cciss_max_sectors;
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BYTE cciss_read;
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BYTE cciss_write;
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BYTE cciss_read_capacity;
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/* information about each logical volume */
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drive_info_struct *drv[CISS_MAX_LUN];
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struct access_method access;
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/* queue and queue Info */
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struct list_head reqQ;
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struct list_head cmpQ;
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unsigned int Qdepth;
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unsigned int maxQsinceinit;
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unsigned int maxSG;
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spinlock_t lock;
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/* pointers to command and error info pool */
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CommandList_struct *cmd_pool;
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dma_addr_t cmd_pool_dhandle;
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ErrorInfo_struct *errinfo_pool;
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dma_addr_t errinfo_pool_dhandle;
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unsigned long *cmd_pool_bits;
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int nr_allocs;
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int nr_frees;
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int busy_configuring;
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int busy_initializing;
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int busy_scanning;
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struct mutex busy_shutting_down;
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/* This element holds the zero based queue number of the last
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* queue to be started. It is used for fairness.
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*/
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int next_to_run;
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/* Disk structures we need to pass back */
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struct gendisk *gendisk[CISS_MAX_LUN];
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#ifdef CONFIG_CISS_SCSI_TAPE
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struct cciss_scsi_adapter_data_t *scsi_ctlr;
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#endif
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unsigned char alive;
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struct list_head scan_list;
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struct completion scan_wait;
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struct device dev;
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/*
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* Performant mode tables.
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*/
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u32 trans_support;
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u32 trans_offset;
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struct TransTable_struct *transtable;
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unsigned long transMethod;
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/*
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* Performant mode completion buffer
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*/
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u64 *reply_pool;
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dma_addr_t reply_pool_dhandle;
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u64 *reply_pool_head;
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size_t reply_pool_size;
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unsigned char reply_pool_wraparound;
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u32 *blockFetchTable;
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};
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/* Defining the diffent access_methods
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*
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* Memory mapped FIFO interface (SMART 53xx cards)
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*/
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#define SA5_DOORBELL 0x20
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#define SA5_REQUEST_PORT_OFFSET 0x40
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#define SA5_REPLY_INTR_MASK_OFFSET 0x34
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#define SA5_REPLY_PORT_OFFSET 0x44
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#define SA5_INTR_STATUS 0x30
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#define SA5_SCRATCHPAD_OFFSET 0xB0
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#define SA5_CTCFG_OFFSET 0xB4
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#define SA5_CTMEM_OFFSET 0xB8
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#define SA5_INTR_OFF 0x08
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#define SA5B_INTR_OFF 0x04
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#define SA5_INTR_PENDING 0x08
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#define SA5B_INTR_PENDING 0x04
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#define FIFO_EMPTY 0xffffffff
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#define CCISS_FIRMWARE_READY 0xffff0000 /* value in scratchpad register */
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/* Perf. mode flags */
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#define SA5_PERF_INTR_PENDING 0x04
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#define SA5_PERF_INTR_OFF 0x05
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#define SA5_OUTDB_STATUS_PERF_BIT 0x01
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#define SA5_OUTDB_CLEAR_PERF_BIT 0x01
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#define SA5_OUTDB_CLEAR 0xA0
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#define SA5_OUTDB_CLEAR_PERF_BIT 0x01
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#define SA5_OUTDB_STATUS 0x9C
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#define CISS_ERROR_BIT 0x02
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#define CCISS_INTR_ON 1
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#define CCISS_INTR_OFF 0
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/* CCISS_BOARD_READY_WAIT_SECS is how long to wait for a board
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* to become ready, in seconds, before giving up on it.
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* CCISS_BOARD_READY_POLL_INTERVAL_MSECS * is how long to wait
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* between polling the board to see if it is ready, in
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* milliseconds. CCISS_BOARD_READY_ITERATIONS is derived
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* the above.
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*/
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#define CCISS_BOARD_READY_WAIT_SECS (120)
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#define CCISS_BOARD_NOT_READY_WAIT_SECS (100)
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#define CCISS_BOARD_READY_POLL_INTERVAL_MSECS (100)
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#define CCISS_BOARD_READY_ITERATIONS \
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((CCISS_BOARD_READY_WAIT_SECS * 1000) / \
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CCISS_BOARD_READY_POLL_INTERVAL_MSECS)
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#define CCISS_BOARD_NOT_READY_ITERATIONS \
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((CCISS_BOARD_NOT_READY_WAIT_SECS * 1000) / \
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CCISS_BOARD_READY_POLL_INTERVAL_MSECS)
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#define CCISS_POST_RESET_PAUSE_MSECS (3000)
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#define CCISS_POST_RESET_NOOP_INTERVAL_MSECS (4000)
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#define CCISS_POST_RESET_NOOP_RETRIES (12)
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#define CCISS_POST_RESET_NOOP_TIMEOUT_MSECS (10000)
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/*
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Send the command to the hardware
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*/
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static void SA5_submit_command( ctlr_info_t *h, CommandList_struct *c)
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{
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#ifdef CCISS_DEBUG
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printk(KERN_WARNING "cciss%d: Sending %08x - down to controller\n",
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h->ctlr, c->busaddr);
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#endif /* CCISS_DEBUG */
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writel(c->busaddr, h->vaddr + SA5_REQUEST_PORT_OFFSET);
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readl(h->vaddr + SA5_SCRATCHPAD_OFFSET);
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h->commands_outstanding++;
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if ( h->commands_outstanding > h->max_outstanding)
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h->max_outstanding = h->commands_outstanding;
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}
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/*
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* This card is the opposite of the other cards.
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* 0 turns interrupts on...
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* 0x08 turns them off...
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*/
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static void SA5_intr_mask(ctlr_info_t *h, unsigned long val)
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{
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if (val)
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{ /* Turn interrupts on */
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h->interrupts_enabled = 1;
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writel(0, h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
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(void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
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} else /* Turn them off */
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{
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h->interrupts_enabled = 0;
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writel( SA5_INTR_OFF,
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h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
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(void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
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}
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}
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/*
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* This card is the opposite of the other cards.
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* 0 turns interrupts on...
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* 0x04 turns them off...
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*/
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static void SA5B_intr_mask(ctlr_info_t *h, unsigned long val)
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{
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if (val)
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{ /* Turn interrupts on */
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h->interrupts_enabled = 1;
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writel(0, h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
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(void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
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} else /* Turn them off */
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{
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h->interrupts_enabled = 0;
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writel( SA5B_INTR_OFF,
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h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
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(void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
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}
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}
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/* Performant mode intr_mask */
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static void SA5_performant_intr_mask(ctlr_info_t *h, unsigned long val)
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{
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if (val) { /* turn on interrupts */
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h->interrupts_enabled = 1;
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writel(0, h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
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(void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
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} else {
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h->interrupts_enabled = 0;
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writel(SA5_PERF_INTR_OFF,
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h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
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(void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
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}
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}
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/*
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* Returns true if fifo is full.
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*
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*/
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static unsigned long SA5_fifo_full(ctlr_info_t *h)
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{
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if( h->commands_outstanding >= h->max_commands)
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return(1);
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else
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return(0);
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}
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/*
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* returns value read from hardware.
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* returns FIFO_EMPTY if there is nothing to read
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*/
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static unsigned long SA5_completed(ctlr_info_t *h)
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{
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unsigned long register_value
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= readl(h->vaddr + SA5_REPLY_PORT_OFFSET);
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if(register_value != FIFO_EMPTY)
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{
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h->commands_outstanding--;
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#ifdef CCISS_DEBUG
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printk("cciss: Read %lx back from board\n", register_value);
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#endif /* CCISS_DEBUG */
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}
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#ifdef CCISS_DEBUG
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else
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{
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printk("cciss: FIFO Empty read\n");
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}
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#endif
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return ( register_value);
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}
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/* Performant mode command completed */
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static unsigned long SA5_performant_completed(ctlr_info_t *h)
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{
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unsigned long register_value = FIFO_EMPTY;
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/* flush the controller write of the reply queue by reading
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* outbound doorbell status register.
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*/
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register_value = readl(h->vaddr + SA5_OUTDB_STATUS);
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/* msi auto clears the interrupt pending bit. */
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if (!(h->msi_vector || h->msix_vector)) {
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writel(SA5_OUTDB_CLEAR_PERF_BIT, h->vaddr + SA5_OUTDB_CLEAR);
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/* Do a read in order to flush the write to the controller
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* (as per spec.)
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*/
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register_value = readl(h->vaddr + SA5_OUTDB_STATUS);
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}
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if ((*(h->reply_pool_head) & 1) == (h->reply_pool_wraparound)) {
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register_value = *(h->reply_pool_head);
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(h->reply_pool_head)++;
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h->commands_outstanding--;
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} else {
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register_value = FIFO_EMPTY;
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}
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/* Check for wraparound */
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if (h->reply_pool_head == (h->reply_pool + h->max_commands)) {
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h->reply_pool_head = h->reply_pool;
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h->reply_pool_wraparound ^= 1;
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}
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return register_value;
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}
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/*
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* Returns true if an interrupt is pending..
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*/
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static bool SA5_intr_pending(ctlr_info_t *h)
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{
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unsigned long register_value =
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readl(h->vaddr + SA5_INTR_STATUS);
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#ifdef CCISS_DEBUG
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printk("cciss: intr_pending %lx\n", register_value);
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#endif /* CCISS_DEBUG */
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if( register_value & SA5_INTR_PENDING)
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return 1;
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return 0 ;
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}
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/*
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* Returns true if an interrupt is pending..
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*/
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static bool SA5B_intr_pending(ctlr_info_t *h)
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{
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unsigned long register_value =
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readl(h->vaddr + SA5_INTR_STATUS);
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#ifdef CCISS_DEBUG
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printk("cciss: intr_pending %lx\n", register_value);
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#endif /* CCISS_DEBUG */
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if( register_value & SA5B_INTR_PENDING)
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return 1;
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return 0 ;
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}
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static bool SA5_performant_intr_pending(ctlr_info_t *h)
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{
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unsigned long register_value = readl(h->vaddr + SA5_INTR_STATUS);
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if (!register_value)
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return false;
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if (h->msi_vector || h->msix_vector)
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return true;
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/* Read outbound doorbell to flush */
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register_value = readl(h->vaddr + SA5_OUTDB_STATUS);
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return register_value & SA5_OUTDB_STATUS_PERF_BIT;
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}
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static struct access_method SA5_access = {
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SA5_submit_command,
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SA5_intr_mask,
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SA5_fifo_full,
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SA5_intr_pending,
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SA5_completed,
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};
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static struct access_method SA5B_access = {
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SA5_submit_command,
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SA5B_intr_mask,
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SA5_fifo_full,
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SA5B_intr_pending,
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SA5_completed,
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};
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static struct access_method SA5_performant_access = {
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SA5_submit_command,
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SA5_performant_intr_mask,
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SA5_fifo_full,
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SA5_performant_intr_pending,
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SA5_performant_completed,
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};
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struct board_type {
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__u32 board_id;
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char *product_name;
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struct access_method *access;
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int nr_cmds; /* Max cmds this kind of ctlr can handle. */
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};
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#endif /* CCISS_H */
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