/******************************************************************************
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*
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* Copyright(c) 2007 - 2017 Realtek Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* The full GNU General Public License is included in this distribution in the
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* file called LICENSE.
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*
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* Contact Information:
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* wlanfae <wlanfae@realtek.com>
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* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
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* Hsinchu 300, Taiwan.
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*
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* Larry Finger <Larry.Finger@lwfinger.net>
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*
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*****************************************************************************/
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#ifndef __ODM_INTERFACE_H__
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#define __ODM_INTERFACE_H__
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#define INTERFACE_VERSION "1.3"
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#define pdm_set_reg odm_set_bb_reg
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/*@=========== Constant/Structure/Enum/... Define*/
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enum phydm_h2c_cmd {
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PHYDM_H2C_RA_MASK = 0x40,
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PHYDM_H2C_TXBF = 0x41,
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ODM_H2C_RSSI_REPORT = 0x42,
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ODM_H2C_IQ_CALIBRATION = 0x45,
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PHYDM_RA_MASK_ABOVE_3SS = 0x46,
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ODM_H2C_RA_PARA_ADJUST = 0x47,
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PHYDM_H2C_DYNAMIC_TX_PATH = 0x48,
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PHYDM_H2C_FW_TRACE_EN = 0x49,
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ODM_H2C_WIFI_CALIBRATION = 0x6d,
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PHYDM_H2C_MU = 0x4a,
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PHYDM_H2C_FW_GENERAL_INIT = 0x4c,
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PHYDM_H2C_FW_CLM_MNTR = 0x4d,
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PHYDM_H2C_MCC = 0x4f,
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PHYDM_H2C_RESP_TX_PATH_CTRL = 0x50,
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PHYDM_H2C_RESP_TX_ANT_CTRL = 0x51,
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PHYDM_H2C_FW_DM_CTRL = 0x55,
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ODM_MAX_H2CCMD
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};
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enum phydm_c2h_evt {
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PHYDM_C2H_DBG = 0,
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PHYDM_C2H_LB = 1,
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PHYDM_C2H_XBF = 2,
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PHYDM_C2H_TX_REPORT = 3,
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PHYDM_C2H_INFO = 9,
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PHYDM_C2H_BT_MP = 11,
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PHYDM_C2H_RA_RPT = 12,
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PHYDM_C2H_RA_PARA_RPT = 14,
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PHYDM_C2H_DYNAMIC_TX_PATH_RPT = 15,
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PHYDM_C2H_IQK_FINISH = 17, /*@0x11*/
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PHYDM_C2H_CLM_MONITOR = 0x2a,
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PHYDM_C2H_DBG_CODE = 0xFE,
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PHYDM_C2H_EXTEND = 0xFF,
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};
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enum phydm_extend_c2h_evt {
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PHYDM_EXTEND_C2H_DBG_PRINT = 0
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};
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enum phydm_halmac_param {
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PHYDM_HALMAC_CMD_MAC_W8 = 0,
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PHYDM_HALMAC_CMD_MAC_W16 = 1,
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PHYDM_HALMAC_CMD_MAC_W32 = 2,
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PHYDM_HALMAC_CMD_BB_W8,
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PHYDM_HALMAC_CMD_BB_W16,
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PHYDM_HALMAC_CMD_BB_W32,
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PHYDM_HALMAC_CMD_RF_W,
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PHYDM_HALMAC_CMD_DELAY_US,
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PHYDM_HALMAC_CMD_DELAY_MS,
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PHYDM_HALMAC_CMD_END = 0XFF,
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};
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/*@=========== Macro Define*/
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#define _reg_all(_name) ODM_##_name
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#define _reg_ic(_name, _ic) ODM_##_name##_ic
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#define _bit_all(_name) BIT_##_name
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#define _bit_ic(_name, _ic) BIT_##_name##_ic
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#if defined(DM_ODM_CE_MAC80211)
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#define ODM_BIT(name, dm) \
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((dm->support_ic_type & ODM_IC_11N_SERIES) ? \
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ODM_BIT_##name##_11N : ODM_BIT_##name##_11AC)
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#define ODM_REG(name, dm) \
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((dm->support_ic_type & ODM_IC_11N_SERIES) ? \
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ODM_REG_##name##_11N : ODM_REG_##name##_11AC)
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#else
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#define _reg_11N(_name) ODM_REG_##_name##_11N
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#define _reg_11AC(_name) ODM_REG_##_name##_11AC
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#define _bit_11N(_name) ODM_BIT_##_name##_11N
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#define _bit_11AC(_name) ODM_BIT_##_name##_11AC
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#ifdef __ECOS
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#define _rtk_cat(_name, _ic_type, _func) \
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( \
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((_ic_type) & ODM_IC_11N_SERIES) ? _func##_11N(_name) : \
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_func##_11AC(_name))
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#else
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#define _cat(_name, _ic_type, _func) \
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( \
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((_ic_type) & ODM_IC_11N_SERIES) ? _func##_11N(_name) : \
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_func##_11AC(_name))
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#endif
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/*@
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* only sample code
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*#define _cat(_name, _ic_type, _func) \
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* ( \
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* ((_ic_type) & ODM_RTL8188E) ? _func##_ic(_name, _8188E) :\
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* _func##_ic(_name, _8195) \
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* )
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*/
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/* @_name: name of register or bit.
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* Example: "ODM_REG(R_A_AGC_CORE1, dm)"
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* gets "ODM_R_A_AGC_CORE1" or "ODM_R_A_AGC_CORE1_8192C",
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* depends on support_ic_type.
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*/
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#ifdef __ECOS
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#define ODM_REG(_name, _pdm_odm) \
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_rtk_cat(_name, _pdm_odm->support_ic_type, _reg)
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#define ODM_BIT(_name, _pdm_odm) \
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_rtk_cat(_name, _pdm_odm->support_ic_type, _bit)
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#else
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#define ODM_REG(_name, _pdm_odm) \
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_cat(_name, _pdm_odm->support_ic_type, _reg)
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#define ODM_BIT(_name, _pdm_odm) \
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_cat(_name, _pdm_odm->support_ic_type, _bit)
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#endif
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#endif
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/*@
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* =========== Extern Variable ??? It should be forbidden.
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*/
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/*@
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* =========== EXtern Function Prototype
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*/
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u8 odm_read_1byte(struct dm_struct *dm, u32 reg_addr);
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u16 odm_read_2byte(struct dm_struct *dm, u32 reg_addr);
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u32 odm_read_4byte(struct dm_struct *dm, u32 reg_addr);
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void odm_write_1byte(struct dm_struct *dm, u32 reg_addr, u8 data);
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void odm_write_2byte(struct dm_struct *dm, u32 reg_addr, u16 data);
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void odm_write_4byte(struct dm_struct *dm, u32 reg_addr, u32 data);
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void odm_set_mac_reg(struct dm_struct *dm, u32 reg_addr, u32 bit_mask,
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u32 data);
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u32 odm_get_mac_reg(struct dm_struct *dm, u32 reg_addr, u32 bit_mask);
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void odm_set_bb_reg(struct dm_struct *dm, u32 reg_addr, u32 bit_mask, u32 data);
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u32 odm_get_bb_reg(struct dm_struct *dm, u32 reg_addr, u32 bit_mask);
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void odm_set_rf_reg(struct dm_struct *dm, u8 e_rf_path, u32 reg_addr,
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u32 bit_mask, u32 data);
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u32 odm_get_rf_reg(struct dm_struct *dm, u8 e_rf_path, u32 reg_addr,
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u32 bit_mask);
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u16 odm_convert_to_le16(u16 value);
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u32 odm_convert_to_le32(u32 value);
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/*@
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* Memory Relative Function.
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*/
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void odm_allocate_memory(struct dm_struct *dm, void **ptr, u32 length);
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void odm_free_memory(struct dm_struct *dm, void *ptr, u32 length);
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void odm_move_memory(struct dm_struct *dm, void *dest, void *src, u32 length);
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s32 odm_compare_memory(struct dm_struct *dm, void *buf1, void *buf2,
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u32 length);
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void odm_memory_set(struct dm_struct *dm, void *pbuf, s8 value, u32 length);
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/*@
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* ODM MISC-spin lock relative API.
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*/
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void odm_acquire_spin_lock(struct dm_struct *dm, enum rt_spinlock_type type);
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void odm_release_spin_lock(struct dm_struct *dm, enum rt_spinlock_type type);
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#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
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/*@
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* ODM MISC-workitem relative API.
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*/
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void odm_initialize_work_item(
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struct dm_struct *dm,
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PRT_WORK_ITEM p_rt_work_item,
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RT_WORKITEM_CALL_BACK rt_work_item_callback,
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void *context,
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const char *sz_id);
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void odm_start_work_item(
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PRT_WORK_ITEM p_rt_work_item);
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void odm_stop_work_item(
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PRT_WORK_ITEM p_rt_work_item);
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void odm_free_work_item(
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PRT_WORK_ITEM p_rt_work_item);
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void odm_schedule_work_item(
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PRT_WORK_ITEM p_rt_work_item);
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boolean
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odm_is_work_item_scheduled(
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PRT_WORK_ITEM p_rt_work_item);
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#endif
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/*@
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* ODM Timer relative API.
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*/
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void ODM_delay_ms(u32 ms);
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void ODM_delay_us(u32 us);
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void ODM_sleep_ms(u32 ms);
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void ODM_sleep_us(u32 us);
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void odm_set_timer(struct dm_struct *dm, struct phydm_timer_list *timer,
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u32 ms_delay);
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void odm_initialize_timer(struct dm_struct *dm, struct phydm_timer_list *timer,
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void *call_back_func, void *context,
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const char *sz_id);
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void odm_cancel_timer(struct dm_struct *dm, struct phydm_timer_list *timer);
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void odm_release_timer(struct dm_struct *dm, struct phydm_timer_list *timer);
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/*ODM FW relative API.*/
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enum hal_status
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phydm_set_reg_by_fw(struct dm_struct *dm, enum phydm_halmac_param config_type,
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u32 offset, u32 data, u32 mask, enum rf_path e_rf_path,
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u32 delay_time);
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void odm_fill_h2c_cmd(struct dm_struct *dm, u8 element_id, u32 cmd_len,
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u8 *cmd_buffer);
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u8 phydm_c2H_content_parsing(void *dm_void, u8 c2h_cmd_id, u8 c2h_cmd_len,
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u8 *tmp_buf);
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u64 odm_get_current_time(struct dm_struct *dm);
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u64 odm_get_progressing_time(struct dm_struct *dm, u64 start_time);
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#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) && \
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(!defined(DM_ODM_CE_MAC80211) && !defined(DM_ODM_CE_MAC80211_V2))
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void phydm_set_hw_reg_handler_interface(struct dm_struct *dm, u8 reg_Name,
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u8 *val);
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void phydm_get_hal_def_var_handler_interface(struct dm_struct *dm,
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enum _HAL_DEF_VARIABLE e_variable,
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void *value);
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#endif
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void odm_set_tx_power_index_by_rate_section(struct dm_struct *dm,
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enum rf_path path, u8 channel,
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u8 rate_section);
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u8 odm_get_tx_power_index(struct dm_struct *dm, enum rf_path path, u8 tx_rate,
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u8 band_width, u8 channel);
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u8 odm_efuse_one_byte_read(struct dm_struct *dm, u16 addr, u8 *data,
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boolean b_pseu_do_test);
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void odm_efuse_logical_map_read(struct dm_struct *dm, u8 type, u16 offset,
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u32 *data);
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enum hal_status
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odm_iq_calibrate_by_fw(struct dm_struct *dm, u8 clear, u8 segment);
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enum hal_status
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odm_dpk_by_fw(struct dm_struct *dm);
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void phydm_cmn_sta_info_hook(struct dm_struct *dm, u8 index,
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struct cmn_sta_info *pcmn_sta_info);
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void phydm_macid2sta_idx_table(struct dm_struct *dm, u8 entry_idx,
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struct cmn_sta_info *pcmn_sta_info);
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void phydm_add_interrupt_mask_handler(struct dm_struct *dm, u8 interrupt_type);
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void phydm_enable_rx_related_interrupt_handler(struct dm_struct *dm);
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void phydm_iqk_wait(struct dm_struct *dm, u32 timeout);
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u8 phydm_get_hwrate_to_mrate(struct dm_struct *dm, u8 rate);
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void phydm_set_crystalcap(struct dm_struct *dm, u8 crystal_cap);
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void phydm_run_in_thread_cmd(struct dm_struct *dm, void (*func)(void *),
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void *context);
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u8 phydm_get_tx_rate(struct dm_struct *dm);
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u8 phydm_get_tx_power_dbm(struct dm_struct *dm, u8 rf_path,
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u8 rate, u8 bandwidth, u8 channel);
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s16 phydm_get_tx_power_mdbm(struct dm_struct *dm, u8 rf_path,
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u8 rate, u8 bandwidth, u8 channel);
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u32 phydm_rfe_ctrl_gpio(struct dm_struct *dm, u8 gpio_num);
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u64 phydm_division64(u64 x, u64 y);
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#endif /* @__ODM_INTERFACE_H__ */
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