/** @file
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Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef __OMAP3530GPMC_H__
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#define __OMAP3530GPMC_H__
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#define GPMC_BASE (0x6E000000)
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//GPMC NAND definitions.
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#define GPMC_SYSCONFIG (GPMC_BASE + 0x10)
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#define SMARTIDLEMODE (0x2UL << 3)
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#define GPMC_SYSSTATUS (GPMC_BASE + 0x14)
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#define GPMC_IRQSTATUS (GPMC_BASE + 0x18)
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#define GPMC_IRQENABLE (GPMC_BASE + 0x1C)
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#define GPMC_TIMEOUT_CONTROL (GPMC_BASE + 0x40)
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#define TIMEOUTENABLE BIT0
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#define TIMEOUTDISABLE (0x0UL << 0)
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#define GPMC_ERR_ADDRESS (GPMC_BASE + 0x44)
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#define GPMC_ERR_TYPE (GPMC_BASE + 0x48)
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#define GPMC_CONFIG (GPMC_BASE + 0x50)
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#define WRITEPROTECT_HIGH BIT4
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#define WRITEPROTECT_LOW (0x0UL << 4)
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#define GPMC_STATUS (GPMC_BASE + 0x54)
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#define GPMC_CONFIG1_0 (GPMC_BASE + 0x60)
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#define DEVICETYPE_NOR (0x0UL << 10)
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#define DEVICETYPE_NAND (0x2UL << 10)
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#define DEVICESIZE_X8 (0x0UL << 12)
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#define DEVICESIZE_X16 BIT12
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#define GPMC_CONFIG2_0 (GPMC_BASE + 0x64)
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#define CSONTIME (0x0UL << 0)
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#define CSRDOFFTIME (0x14UL << 8)
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#define CSWROFFTIME (0x14UL << 16)
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#define GPMC_CONFIG3_0 (GPMC_BASE + 0x68)
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#define ADVRDOFFTIME (0x14UL << 8)
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#define ADVWROFFTIME (0x14UL << 16)
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#define GPMC_CONFIG4_0 (GPMC_BASE + 0x6C)
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#define OEONTIME BIT0
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#define OEOFFTIME (0xFUL << 8)
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#define WEONTIME BIT16
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#define WEOFFTIME (0xFUL << 24)
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#define GPMC_CONFIG5_0 (GPMC_BASE + 0x70)
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#define RDCYCLETIME (0x14UL << 0)
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#define WRCYCLETIME (0x14UL << 8)
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#define RDACCESSTIME (0xCUL << 16)
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#define PAGEBURSTACCESSTIME BIT24
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#define GPMC_CONFIG6_0 (GPMC_BASE + 0x74)
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#define CYCLE2CYCLESAMECSEN BIT7
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#define CYCLE2CYCLEDELAY (0xAUL << 8)
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#define WRDATAONADMUXBUS (0xFUL << 16)
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#define WRACCESSTIME BIT24
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#define GPMC_CONFIG7_0 (GPMC_BASE + 0x78)
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#define BASEADDRESS (0x30UL << 0)
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#define CSVALID BIT6
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#define MASKADDRESS_128MB (0x8UL << 8)
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#define GPMC_NAND_COMMAND_0 (GPMC_BASE + 0x7C)
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#define GPMC_NAND_ADDRESS_0 (GPMC_BASE + 0x80)
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#define GPMC_NAND_DATA_0 (GPMC_BASE + 0x84)
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#define GPMC_ECC_CONFIG (GPMC_BASE + 0x1F4)
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#define ECCENABLE BIT0
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#define ECCDISABLE (0x0UL << 0)
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#define ECCCS_0 (0x0UL << 1)
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#define ECC16B BIT7
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#define GPMC_ECC_CONTROL (GPMC_BASE + 0x1F8)
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#define ECCPOINTER_REG1 BIT0
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#define ECCCLEAR BIT8
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#define GPMC_ECC_SIZE_CONFIG (GPMC_BASE + 0x1FC)
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#define ECCSIZE0_512BYTES (0xFFUL << 12)
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#define ECCSIZE1_512BYTES (0xFFUL << 22)
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#define GPMC_ECC1_RESULT (GPMC_BASE + 0x200)
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#define GPMC_ECC2_RESULT (GPMC_BASE + 0x204)
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#define GPMC_ECC3_RESULT (GPMC_BASE + 0x208)
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#define GPMC_ECC4_RESULT (GPMC_BASE + 0x20C)
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#define GPMC_ECC5_RESULT (GPMC_BASE + 0x210)
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#define GPMC_ECC6_RESULT (GPMC_BASE + 0x214)
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#define GPMC_ECC7_RESULT (GPMC_BASE + 0x218)
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#define GPMC_ECC8_RESULT (GPMC_BASE + 0x21C)
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#define GPMC_ECC9_RESULT (GPMC_BASE + 0x220)
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#endif //__OMAP3530GPMC_H__
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