/* SPDX-License-Identifier: BSD-3-Clause */
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/*
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* Copyright (c) 2020-2021 Rockchip Electronics Co., Ltd.
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*/
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#include "Soc.h"
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#include <Library/DebugLib.h>
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#include <Library/IoLib.h>
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#include <Library/PcdLib.h>
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#include <Library/TimerLib.h>
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#include <Library/SpiMem.h>
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#include <Library/Fspi.h>
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#define HAL_IS_ALIGNED(x, a) (((x) & (a - 1)) == 0)
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/********************* Private MACRO Definition ******************************/
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// #define FSPI_DEBUG
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#ifdef FSPI_DEBUG
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#define FSPI_DBG(...)
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#else
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#define FSPI_DBG(...)
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#endif
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/* FSPI_CTRL */
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#define FSPI_CTRL_SHIFTPHASE_NEGEDGE 1
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/* FSPI_RCVR */
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#define FSPI_RCVR_RCVR_RESET (1 << FSPI_RCVR_RCVR_SHIFT) /* Recover The FSPI State Machine */
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/* FSPI_ISR */
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#define FSPI_ISR_DMAS_ACTIVE (1 << FSPI_ISR_DMAS_SHIFT) /* DMA Finish Interrupt Active */
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#define FSPI_ISR_NSPIS_ACTIVE (1 << FSPI_ISR_NSPIS_SHIFT) /* SPI Error Interrupt Active */
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#define FSPI_ISR_AHBS_ACTIVE (1 << FSPI_ISR_AHBS_SHIFT) /* AHB Error Interrupt Active */
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#define FSPI_ISR_TRANSS_ACTIVE (1 << FSPI_ISR_TRANSS_SHIFT) /* Transfer finish Interrupt Active */
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#define FSPI_ISR_TXES_ACTIVE (1 << FSPI_ISR_TXES_SHIFT) /* Transmit FIFO Empty Interrupt Active */
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#define FSPI_ISR_TXOS_ACTIVE (1 << FSPI_ISR_TXOS_SHIFT) /* Transmit FIFO Overflow Interrupt Active */
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#define FSPI_ISR_RXUS_ACTIVE (1 << FSPI_ISR_RXUS_SHIFT) /* Receive FIFO Underflow Interrupt Active */
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#define FSPI_ISR_RXFS_ACTIVE (1 << FSPI_ISR_RXFS_SHIFT) /* Receive FIFO Full Interrupt Active */
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/* FSPI_FSR */
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#define FSPI_FSR_RXFS_EMPTY (1 << FSPI_FSR_RXFS_SHIFT) /* Receive FIFO Full */
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#define FSPI_FSR_RXES_EMPTY (1 << FSPI_FSR_RXES_SHIFT) /* Receive FIFO Empty */
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#define FSPI_FSR_TXFS_FULL (1 << FSPI_FSR_TXFS_SHIFT) /* Transmit FIFO Full */
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#define FSPI_FSR_TXES_EMPTY (1 << FSPI_FSR_TXES_SHIFT) /* Transmit FIFO Empty */
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/* FSPI_SR */
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#define FSPI_SR_SR_BUSY (1 << FSPI_SR_SR_SHIFT) /* When busy, do not set the control register. */
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/* FSPI_DMATR */
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#define FSPI_DMATR_DMATR_START (1 << FSPI_DMATR_DMATR_SHIFT) /* Write 1 to start the dma transfer. */
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/* FSPI_RISR */
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#define FSPI_RISR_TRANSS_ACTIVE (1 << FSPI_RISR_TRANSS_SHIFT)
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/* FSPI attributes */
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#define FSPI_VER_VER_1 1
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#define FSPI_VER_VER_3 3
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#define FSPI_VER_VER_5 5
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#define FSPI_NOR_FLASH_PAGE_SIZE 0x100
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#define FSPI_MAX_IOSIZE_VER3 (1024U * 8)
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#define FSPI_MAX_IOSIZE_VER4 (0xFFFFFFFFU)
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/********************* Private Structure Definition **************************/
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typedef union {
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UINT32 d32;
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struct {
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unsigned txempty : 1; /* tx fifo empty */
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unsigned txfull : 1; /* tx fifo full */
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unsigned rxempty : 1; /* rx fifo empty */
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unsigned rxfull : 1; /* tx fifo empty interrupt mask */
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unsigned reserved7_4 : 4;
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unsigned txlevel : 5; /* tx fifo: 0: full; 1: left 1 entry; ... */
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unsigned reserved15_13 : 3;
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unsigned rxlevel : 5; /* rx fifo: 0: full; 1: left 1 entry; ... */
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unsigned reserved31_21 : 11;
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} b;
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} FSPIFSR_DATA;
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/** FSPI_XMMC bit union */
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typedef union {
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UINT32 d32;
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struct {
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unsigned reserverd1 : 5;
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unsigned devHwEn : 1; /* device Hwrite Enable */
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unsigned prefetch : 1; /* prefetch enable */
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unsigned uincrPrefetchEn : 1; /* undefine INCR Burst Prefetch Enable */
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unsigned uincrLen : 4; /* undefine INCR length */
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unsigned devWrapEn : 1; /* device Wrap Enable */
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unsigned devIncrEn : 1; /* device INCR2/4/8/16 Enable */
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unsigned devUdfincrEn : 1; /* device Undefine INCR Enable */
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unsigned reserved2 : 17;
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} b;
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} FSPIXMMCCTRL_DATA;
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/********************* Private Variable Definition ***************************/
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/********************* Private Function Definition ***************************/
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static void FSPI_Reset(struct HAL_FSPI_HOST *host)
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{
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INT32 timeout = 10000;
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host->instance->RCVR = FSPI_RCVR_RCVR_RESET;
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while ((host->instance->RCVR == FSPI_RCVR_RCVR_RESET) && (timeout > 0)) {
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HAL_CPUDelayUs(1);
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timeout--;
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}
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host->instance->ICLR = 0xFFFFFFFF;
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}
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static void FSPI_ContModeInit(struct HAL_FSPI_HOST *host)
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{
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/* Setup when FSPI->AX = 0xa5, Cancel when FSPI->AX = 0x0 */
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WRITE_REG(host->instance->EXT_AX, 0xa5 << FSPI_EXT_AX_AX_SETUP_PAT_SHIFT |
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0x5a << FSPI_EXT_AX_AX_CANCEL_PAT_SHIFT);
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/* Skip Continuous mode in default */
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switch (host->cs) {
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case 0:
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WRITE_REG(host->instance->AX0, 0 << FSPI_AX0_AX_SHIFT);
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break;
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case 1:
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WRITE_REG(host->instance->AX1, 0 << FSPI_AX1_AX_SHIFT);
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break;
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default:
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break;
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}
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}
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static void FSPI_ContModeDeInit(struct HAL_FSPI_HOST *host)
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{
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/* FSPI avoid setup pattern match with FSPI->AX */
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WRITE_REG(host->instance->EXT_AX, 0x77 << FSPI_EXT_AX_AX_SETUP_PAT_SHIFT |
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0x88 << FSPI_EXT_AX_AX_CANCEL_PAT_SHIFT);
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}
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/**
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* @brief Configuration register with flash operation protocol.
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* @param host: FSPI host.
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* @param op: flash operation protocol.
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* @return RETURN_STATUS.
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* @attention Set host->cs to select chip.
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*/
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RETURN_STATUS HAL_FSPI_XferStart(struct HAL_FSPI_HOST *host, struct HAL_SPI_MEM_OP *op)
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{
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struct FSPI_REG *pReg = host->instance;
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FSPICMD_DATA FSPICmd;
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FSPICTRL_DATA FSPICtrl;
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FSPICmd.d32 = 0;
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FSPICtrl.d32 = 0;
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/* set CMD */
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FSPICmd.b.cmd = op->cmd.opcode;
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if (op->cmd.buswidth == 4) {
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FSPICtrl.b.cmdlines = FSPI_LINES_X4;
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FSPICtrl.b.datalines = FSPI_LINES_X4; /* cmdlines work with datalines */
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}
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/* set ADDR */
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if (op->addr.nbytes) {
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if (op->addr.nbytes == 4) {
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FSPICmd.b.addrbits = FSPI_ADDR_32BITS;
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} else if (op->addr.nbytes == 3) {
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FSPICmd.b.addrbits = FSPI_ADDR_24BITS;
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} else {
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FSPICmd.b.addrbits = FSPI_ADDR_XBITS;
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pReg->ABIT0 = op->addr.nbytes * 8 - 1;
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}
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FSPICtrl.b.addrlines = op->addr.buswidth == 4 ? FSPI_LINES_X4 : FSPI_LINES_X1;
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}
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/* set DUMMY*/
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if (op->dummy.nbytes) {
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switch (op->dummy.buswidth) {
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case 4:
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FSPICmd.b.dummybits = op->dummy.nbytes * 2;
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break;
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case 2:
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FSPICmd.b.dummybits = op->dummy.nbytes * 4;
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break;
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default:
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FSPICmd.b.dummybits = op->dummy.nbytes * 8;
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break;
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}
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}
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/* set DATA */
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WRITE_REG(pReg->LEN_EXT, op->data.nbytes);
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if (op->data.nbytes) {
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if (op->data.dir == HAL_SPI_MEM_DATA_OUT) {
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FSPICmd.b.rw = FSPI_WRITE;
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}
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if (op->data.buswidth == 4) {
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FSPICtrl.b.datalines = FSPI_LINES_X4;
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} else if (op->data.buswidth == 2) {
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FSPICtrl.b.datalines = FSPI_LINES_X2;
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} else {
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FSPICtrl.b.datalines = FSPI_LINES_X1;
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}
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}
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/* spitial setting */
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FSPICtrl.b.sps = host->mode & HAL_SPI_CPHA;
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FSPICmd.b.cs = host->cs;
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if (op->data.nbytes == 0 && op->addr.nbytes) {
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FSPICmd.b.rw = FSPI_WRITE;
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}
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if (!(pReg->FSR & FSPI_FSR_TXES_EMPTY) || !(pReg->FSR & FSPI_FSR_RXES_EMPTY) || (pReg->SR & FSPI_SR_SR_BUSY)) {
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FSPI_Reset(host);
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}
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// FSPI_DBG("%s 1 %x %x %x\n", __func__, op->addr.nbytes, op->dummy.nbytes, op->data.nbytes);
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// FSPI_DBG("%s 2 %lx %lx %lx %x\n", __func__, FSPICtrl.d32, FSPICmd.d32, op->addr.val, host->cs);
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/* config FSPI */
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switch (host->cs) {
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case 0:
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pReg->CTRL0 = FSPICtrl.d32;
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break;
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case 1:
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pReg->CTRL1 = FSPICtrl.d32;
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break;
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default:
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break;
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}
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pReg->CMD = FSPICmd.d32;
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if (op->addr.nbytes) {
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pReg->ADDR = op->addr.val;
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}
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return RETURN_SUCCESS;
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}
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/**
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* @brief IO transfer.
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* @param host: FSPI host.
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* @param len: data n bytes.
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* @param data: transfer buffer.
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* @param dir: transfer direction.
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* @return RETURN_STATUS.
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*/
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RETURN_STATUS HAL_FSPI_XferData(struct HAL_FSPI_HOST *host, UINT32 len, void *data, UINT32 dir)
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{
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RETURN_STATUS ret = RETURN_SUCCESS;
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__IO FSPIFSR_DATA fifostat;
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INT32 timeout = 0;
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UINT32 i, words;
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UINT32 *pData = (UINT32 *)data;
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struct FSPI_REG *pReg = host->instance;
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UINT32 temp = 0;
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HAL_ASSERT(data && len);
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if (len && len < 4 && dir == FSPI_WRITE) {
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if (len == 1) {
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temp = *((uint8_t *)data);
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} else if (len == 2) {
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temp = *((uint16_t *)data);
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} else {
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temp = ((uint8_t *)data)[0] | ((uint8_t *)data)[1] << 8 | ((uint8_t *)data)[2] << 16;
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}
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pData = &temp;
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} else if (len >= 4 && !HAL_IS_ALIGNED((long)data, 4)) {
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FSPI_DBG("%s data unaligned access\n", __func__);
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}
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/* FSPI_DBG("%s %p len %lx word0 %lx dir %lx\n", __func__, pData, len, pData[0], dir); */
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if (dir == FSPI_WRITE) {
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words = (len + 3) >> 2;
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while (words) {
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fifostat.d32 = pReg->FSR;
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if (fifostat.b.txlevel > 0) {
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UINT32 count = MIN(words, fifostat.b.txlevel);
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for (i = 0; i < count; i++) {
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pReg->DATA = *pData++;
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words--;
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}
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if (words == 0) {
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break;
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}
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timeout = 0;
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} else {
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HAL_CPUDelayUs(1);
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if (timeout++ > 10000) {
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ret = RETURN_TIMEOUT;
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break;
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}
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}
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}
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} else {
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UINT32 bytes = len & 0x3;
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words = len >> 2;
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while (words) {
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fifostat.d32 = pReg->FSR;
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if (fifostat.b.rxlevel > 0) {
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UINT32 count = MIN(words, fifostat.b.rxlevel);
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if (count == 15) { /* Reduce CPU cost */
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*pData++ = pReg->DATA;
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*pData++ = pReg->DATA;
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*pData++ = pReg->DATA;
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*pData++ = pReg->DATA;
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*pData++ = pReg->DATA;
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*pData++ = pReg->DATA;
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*pData++ = pReg->DATA;
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*pData++ = pReg->DATA;
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*pData++ = pReg->DATA;
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*pData++ = pReg->DATA;
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*pData++ = pReg->DATA;
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*pData++ = pReg->DATA;
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*pData++ = pReg->DATA;
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*pData++ = pReg->DATA;
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*pData++ = pReg->DATA;
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words -= 15;
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} else {
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for (i = 0; i < count; i++) {
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*pData++ = pReg->DATA;
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}
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words -= count;
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}
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if (0 == words) {
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break;
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}
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timeout = 0;
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} else {
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HAL_CPUDelayUs(1);
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if (timeout++ > 10000) {
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ret = RETURN_TIMEOUT;
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break;
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}
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}
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}
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timeout = 0;
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while (bytes) {
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fifostat.d32 = pReg->FSR;
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if (fifostat.b.rxlevel > 0) {
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uint8_t *pData1 = (uint8_t *)pData;
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words = pReg->DATA;
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for (i = 0; i < bytes; i++) {
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pData1[i] = (uint8_t)((words >> (i * 8)) & 0xFF);
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}
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break;
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} else {
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HAL_CPUDelayUs(1);
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if (timeout++ > 10000) {
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ret = RETURN_TIMEOUT;
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break;
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}
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}
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}
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}
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return ret;
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}
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/**
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* @brief Wait for FSPI host transfer finished.
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* @return RETURN_STATUS.
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*/
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RETURN_STATUS HAL_FSPI_XferDone(struct HAL_FSPI_HOST *host)
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{
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RETURN_STATUS ret = RETURN_SUCCESS;
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INT32 timeout = 0;
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struct FSPI_REG *pReg = host->instance;
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while (pReg->SR & FSPI_SR_SR_BUSY) {
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HAL_CPUDelayUs(1);
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if (timeout++ > 100000) { /*wait 100ms*/
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ret = RETURN_TIMEOUT;
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break;
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}
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}
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HAL_CPUDelayUs(1); //CS# High Time (read/write) >100ns
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return ret;
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}
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/**
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* @brief SPI Nor flash data transmission interface to support open source specifications SNOR.
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* @param host: FSPI host.
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* @param op: flash operation protocol.
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* @return RETURN_STATUS.
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* @attention Set host->cs to select chip.
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*/
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RETURN_STATUS HAL_FSPI_SpiXfer(struct HAL_FSPI_HOST *host, struct HAL_SPI_MEM_OP *op)
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{
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RETURN_STATUS ret = RETURN_SUCCESS;
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UINT32 dir = op->data.dir;
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void *pData = NULL;
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HAL_ASSERT(IS_FSPI_INSTANCE(host->instance));
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if (op->data.buf.in) {
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pData = (void *)op->data.buf.in;
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} else if (op->data.buf.out) {
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pData = (void *)op->data.buf.out;
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}
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HAL_FSPI_XferStart(host, op);
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if (pData) {
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ret = HAL_FSPI_XferData(host, op->data.nbytes, pData, dir);
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if (ret) {
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FSPI_DBG("%s xfer data failed ret %d\n", __func__, ret);
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return ret;
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}
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}
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return HAL_FSPI_XferDone(host);
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}
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/** @} */
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/** @defgroup FSPI_Exported_Functions_Group4 Init and DeInit Functions
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This section provides functions allowing to init and deinit the module:
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* @{
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*/
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/**
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* @brief Init FSPI.
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* @param host: FSPI host.
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* @return RETURN_STATUS.
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*/
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RETURN_STATUS HAL_FSPI_Init(struct HAL_FSPI_HOST *host)
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{
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INT32 timeout = 0;
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struct FSPI_REG *pReg;
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RETURN_STATUS ret = RETURN_SUCCESS;
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HAL_ASSERT(IS_FSPI_INSTANCE(host->instance));
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pReg = host->instance;
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pReg->MODE = 0;
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while (pReg->SR & FSPI_SR_SR_BUSY) {
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HAL_CPUDelayUs(1);
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if (timeout++ > 1000) {
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return RETURN_TIMEOUT;
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}
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}
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FSPI_ContModeInit(host);
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pReg->CTRL0 = 0;
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#if (FSPI_VER > FSPI_VER_VER_3)
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WRITE_REG(pReg->LEN_CTRL, FSPI_LEN_CTRL_TRB_SEL_MASK);
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#endif
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return ret;
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}
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/**
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* @brief DeInit FSPI.
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* @param host: FSPI host.
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* @return RETURN_STATUS.
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*/
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RETURN_STATUS HAL_FSPI_DeInit(struct HAL_FSPI_HOST *host)
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{
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HAL_ASSERT(IS_FSPI_INSTANCE(host->instance));
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host->instance->MODE = 0;
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FSPI_ContModeDeInit(host);
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FSPI_Reset(host);
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return RETURN_SUCCESS;
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}
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/**
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* @brief Set FSPI delay line.
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* @param host: FSPI host.
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* @param cells: delay line cells.
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* @return RETURN_STATUS.
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*/
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RETURN_STATUS HAL_FSPI_SetDelayLines(struct HAL_FSPI_HOST *host, uint8_t cells)
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{
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HAL_ASSERT(IS_FSPI_INSTANCE(host->instance));
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if (host->cs == 0) {
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WRITE_REG(host->instance->DLL_CTRL0, 1 << FSPI_DLL_CTRL0_SCLK_SMP_SEL_SHIFT | cells);
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} else {
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WRITE_REG(host->instance->DLL_CTRL1, 1 << FSPI_DLL_CTRL0_SCLK_SMP_SEL_SHIFT | cells);
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}
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return RETURN_SUCCESS;
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}
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UINT32 HAL_FSPI_GetMaxIoSize(struct HAL_FSPI_HOST *host)
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{
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HAL_ASSERT(IS_FSPI_INSTANCE(host->instance));
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return FSPI_MAX_IOSIZE_VER4;
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}
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