//------------------------------------------------------------------------------
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//
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// RISC-V CPU functions.
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//
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// Copyright (c) 2016 - 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
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//
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// SPDX-License-Identifier: BSD-2-Clause-Patent
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//
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//------------------------------------------------------------------------------
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#include <Base.h>
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#include <RiscVImpl.h>
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.data
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.text
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.align 3
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//
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// Set machine mode scratch.
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// @param a0 : Pointer to RISCV_MACHINE_MODE_CONTEXT.
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//
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ASM_FUNC (RiscVSetMachineScratch)
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csrrw a1, RISCV_CSR_MACHINE_MSCRATCH, a0
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ret
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//
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// Get machine mode scratch.
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// @retval a0 : Pointer to RISCV_MACHINE_MODE_CONTEXT.
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//
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ASM_FUNC (RiscVGetMachineScratch)
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csrrs a0, RISCV_CSR_MACHINE_MSCRATCH, 0
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ret
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//
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// Get machine trap cause CSR.
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//
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ASM_FUNC (RiscVGetMachineTrapCause)
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csrrs a0, RISCV_CSR_MACHINE_MCAUSE, 0
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ret
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//
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// Get machine interrupt enable
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//
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ASM_FUNC (RiscVReadMachineInterruptEnable)
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csrr a0, RISCV_CSR_MACHINE_MIE
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ret
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//
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// Get machine interrupt pending
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//
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ASM_FUNC (RiscVReadMachineInterruptPending)
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csrr a0, RISCV_CSR_MACHINE_MIP
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ret
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//
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// Get machine status
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//
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ASM_FUNC (RiscVReadMachineStatus)
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csrr a0, RISCV_CSR_MACHINE_MSTATUS
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ret
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//
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// Set machine status
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//
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ASM_FUNC (RiscVWriteMachineStatus)
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csrw RISCV_CSR_MACHINE_MSTATUS, a0
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ret
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//
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// Get machine trap vector
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//
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ASM_FUNC (RiscVReadMachineTrapVector)
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csrr a0, RISCV_CSR_MACHINE_MTVEC
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ret
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//
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// Read machine ISA
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//
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ASM_FUNC (RiscVReadMachineIsa)
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csrr a0, RISCV_CSR_MACHINE_MISA
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ret
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//
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// Read machine vendor ID
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//
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ASM_FUNC (RiscVReadMachineVendorId)
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csrr a0, RISCV_CSR_MACHINE_MVENDORID
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ret
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//
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// Read machine architecture ID
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//
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ASM_FUNC (RiscVReadMachineArchitectureId)
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csrr a0, RISCV_CSR_MACHINE_MARCHID
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ret
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//
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// Read machine implementation ID
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//
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ASM_FUNC (RiscVReadMachineImplementId)
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csrr a0, RISCV_CSR_MACHINE_MIMPID
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ret
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//
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// Set Supervisor Address Translation and
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// Protection Register.
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//
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ASM_FUNC (RiscVSetSupervisorAddressTranslationRegister)
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csrw RISCV_CSR_SUPERVISOR_SATP, a0
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ret
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