/** @file
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This driver installs SMBIOS information for Marvell Armada platforms
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Copyright (c) 2015-2020, Arm Limited. All rights reserved.<BR>
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Copyright (c) 2019, Marvell International Ltd. and its affiliates
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#include <Library/BaseLib.h>
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#include <Library/BaseMemoryLib.h>
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#include <Library/DebugLib.h>
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#include <Library/HobLib.h>
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#include <Library/MemoryAllocationLib.h>
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#include <Library/PcdLib.h>
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#include <Library/SampleAtResetLib.h>
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#include <Library/UefiBootServicesTableLib.h>
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#include <Protocol/Smbios.h>
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#include <IndustryStandard/SmBios.h>
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//
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// SMBIOS tables often reference each other using
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// fixed constants, define a list of these constants
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// for our hardcoded tables
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//
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enum SMBIOS_REFRENCE_HANDLES {
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SMBIOS_HANDLE_A72_L1I = 0x1000,
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SMBIOS_HANDLE_A72_L1D,
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SMBIOS_HANDLE_A72_L2,
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SMBIOS_HANDLE_L3,
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SMBIOS_HANDLE_MOTHERBOARD,
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SMBIOS_HANDLE_CHASSIS,
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SMBIOS_HANDLE_A72_CLUSTER,
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SMBIOS_HANDLE_MEMORY,
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SMBIOS_HANDLE_DIMM
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};
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//
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// Type definition and contents of the default SMBIOS table.
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// This table covers only the minimum structures required by
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// the SMBIOS specification (section 6.2, version 3.0)
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//
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// BIOS information (section 7.1)
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STATIC SMBIOS_TABLE_TYPE0 mArmadaDefaultType0 = {
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{ // SMBIOS_STRUCTURE Hdr
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EFI_SMBIOS_TYPE_BIOS_INFORMATION, // UINT8 Type
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sizeof (SMBIOS_TABLE_TYPE0), // UINT8 Length
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SMBIOS_HANDLE_PI_RESERVED,
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},
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1, // SMBIOS_TABLE_STRING Vendor
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2, // SMBIOS_TABLE_STRING BiosVersion
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0xE800,// UINT16 BiosSegment
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3, // SMBIOS_TABLE_STRING BiosReleaseDate
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0, // UINT8 BiosSize
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{
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0,0,0,0,0,0,
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1, //PCI supported
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0,
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1, //PNP supported
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0,
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1, //BIOS upgradable
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0, 0, 0,
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0, //Boot from CD
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1, //selectable boot
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}, // MISC_BIOS_CHARACTERISTICS BiosCharacteristics
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{ // BIOSCharacteristicsExtensionBytes[2]
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0x3,
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0xC,
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},
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0, // UINT8 SystemBiosMajorRelease
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0, // UINT8 SystemBiosMinorRelease
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0xFF, // UINT8 EmbeddedControllerFirmwareMajorRelease
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0xFF, // UINT8 EmbeddedControllerFirmwareMinorRelease
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};
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STATIC CHAR8 CONST *mArmadaDefaultType0Strings[] = {
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(CHAR8 CONST *)PcdGetPtr (PcdFirmwareVendor), /* Vendor */
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(CHAR8 CONST *)PcdGetPtr (PcdFirmwareVersion), /* BiosVersion */
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__DATE__"\0", /* BiosReleaseDate */
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NULL
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};
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// System information (section 7.2)
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STATIC SMBIOS_TABLE_TYPE1 mArmadaDefaultType1 = {
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{ // SMBIOS_STRUCTURE Hdr
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EFI_SMBIOS_TYPE_SYSTEM_INFORMATION,
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sizeof (SMBIOS_TABLE_TYPE1),
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SMBIOS_HANDLE_PI_RESERVED,
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},
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1, //Manufacturer
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2, //Product Name
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3, //Version
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4, //Serial
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{ 0x97c93925, 0x1273, 0x4f03, { 0x9f,0x75,0x2f,0x2b,0x7e,0xd1,0x94,0x80 }}, //UUID
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6, //Wakeup type
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0, //SKU
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0, //Family
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};
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STATIC CHAR8 CONST *mArmadaDefaultType1Strings[] = {
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(CHAR8 CONST *)PcdGetPtr (PcdProductManufacturer),
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(CHAR8 CONST *)PcdGetPtr (PcdProductPlatformName),
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(CHAR8 CONST *)PcdGetPtr (PcdProductVersion),
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(CHAR8 CONST *)PcdGetPtr (PcdProductSerial),
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NULL
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};
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// Baseboard (section 7.3)
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STATIC SMBIOS_TABLE_TYPE2 mArmadaDefaultType2 = {
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{ // SMBIOS_STRUCTURE Hdr
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EFI_SMBIOS_TYPE_BASEBOARD_INFORMATION, // UINT8 Type
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sizeof (SMBIOS_TABLE_TYPE2), // UINT8 Length
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SMBIOS_HANDLE_MOTHERBOARD,
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},
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1, //Manufacturer
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2, //Product Name
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3, //Version
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4, //Serial
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0, //Asset tag
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{1}, //motherboard, not replaceable
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5, //location of board
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SMBIOS_HANDLE_CHASSIS,
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BaseBoardTypeMotherBoard,
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1,
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{SMBIOS_HANDLE_A72_CLUSTER},
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};
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STATIC CHAR8 CONST *mArmadaDefaultType2Strings[] = {
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(CHAR8 CONST *)PcdGetPtr (PcdProductManufacturer),
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(CHAR8 CONST *)PcdGetPtr (PcdProductPlatformName),
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(CHAR8 CONST *)PcdGetPtr (PcdProductVersion),
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(CHAR8 CONST *)PcdGetPtr (PcdProductSerial),
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"Base of Chassis \0",/* Board location */
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NULL
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};
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// Enclosure
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STATIC SMBIOS_TABLE_TYPE3 mArmadaDefaultType3 = {
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{ // SMBIOS_STRUCTURE Hdr
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EFI_SMBIOS_TYPE_SYSTEM_ENCLOSURE, // UINT8 Type
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sizeof (SMBIOS_TABLE_TYPE3), // UINT8 Length
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SMBIOS_HANDLE_CHASSIS,
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},
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1, //Manufacturer
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2, //enclosure type
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2, //version
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3, //serial
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0, //asset tag
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ChassisStateUnknown, //boot chassis state
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ChassisStateSafe, //power supply state
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ChassisStateSafe, //thermal state
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ChassisSecurityStatusNone, //security state
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{0,0,0,0,}, //OEM defined
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1, //1U height
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1, //number of power cords
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0, //no contained elements
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};
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STATIC CHAR8 CONST *mArmadaDefaultType3Strings[] = {
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(CHAR8 CONST *)PcdGetPtr (PcdProductManufacturer),
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(CHAR8 CONST *)PcdGetPtr (PcdProductVersion),
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(CHAR8 CONST *)PcdGetPtr (PcdProductSerial),
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NULL
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};
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// Processor
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STATIC SMBIOS_TABLE_TYPE4 mArmadaDefaultType4 = {
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{ // SMBIOS_STRUCTURE Hdr
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EFI_SMBIOS_TYPE_PROCESSOR_INFORMATION, // UINT8 Type
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sizeof (SMBIOS_TABLE_TYPE4), // UINT8 Length
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SMBIOS_HANDLE_A72_CLUSTER,
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},
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1, //socket type
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3, //processor type CPU
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ProcessorFamilyIndicatorFamily2, //processor family, acquire from field2
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2, //manufactuer
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{{0,},{0.}}, //processor id
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3, //version
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{0,0,0,0,0,1}, //voltage
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0, //external clock
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2200, //max speed
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0, //current speed - requires update
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0x41, //status
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ProcessorUpgradeOther,
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SMBIOS_HANDLE_A72_L1I, //l1 cache handle
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SMBIOS_HANDLE_A72_L2, //l2 cache handle
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SMBIOS_HANDLE_L3, //l3 cache handle
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0, //serial not set
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0, //asset not set
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4, //part number
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4, //core count in socket
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4, //enabled core count in socket
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4, //threads per socket
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0xEC, //processor characteristics
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ProcessorFamilyARM, //ARM core
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0, // CoreCount2;
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0, // EnabledCoreCount2;
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0, // ThreadCount2;
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};
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STATIC CHAR8 CONST *mArmadaDefaultType4Strings[] = {
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"Socket type unknown \0", /* Socket type placeholder */
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"Marvell\0", /* manufactuer */
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"Cortex-A72\0", /* processor description */
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"0xd08\0", /* A72 part number */
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NULL
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};
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// Cache
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STATIC SMBIOS_TABLE_TYPE7 mArmadaDefaultType7_a72_l1i = {
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{ // SMBIOS_STRUCTURE Hdr
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EFI_SMBIOS_TYPE_CACHE_INFORMATION, // UINT8 Type
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sizeof (SMBIOS_TABLE_TYPE7), // UINT8 Length
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SMBIOS_HANDLE_A72_L1I,
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},
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1,
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0x380, //L1 enabled, unknown WB
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48, //48k I-cache max
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48, //48k installed
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{0,1}, //SRAM type
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{0,1}, //SRAM type
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0, //speed unknown
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CacheErrorParity, //parity checking
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CacheTypeInstruction, //instruction cache
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CacheAssociativityOther, //three way
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// SMBIOS 3.1.0 fields
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48, //48k I-cache max
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48, //48k installed
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};
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STATIC SMBIOS_TABLE_TYPE7 mArmadaDefaultType7_a72_l1d = {
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{ // SMBIOS_STRUCTURE Hdr
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EFI_SMBIOS_TYPE_CACHE_INFORMATION, // UINT8 Type
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sizeof (SMBIOS_TABLE_TYPE7), // UINT8 Length
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SMBIOS_HANDLE_A72_L1D,
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},
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2,
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0x380, //L1 enabled, unknown WB
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32, //32k D-cache max
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32, //32k installed
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{0,1}, //SRAM type
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{0,1}, //SRAM type
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0, //speed unknown
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CacheErrorSingleBit, //ECC checking
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CacheTypeData, //data cache
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CacheAssociativity2Way, //two way
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// SMBIOS 3.1.0 fields
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32, //32k D-cache max
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32, //32k installed
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};
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STATIC SMBIOS_TABLE_TYPE7 mArmadaDefaultType7_a72_l2 = {
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{ // SMBIOS_STRUCTURE Hdr
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EFI_SMBIOS_TYPE_CACHE_INFORMATION, // UINT8 Type
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sizeof (SMBIOS_TABLE_TYPE7), // UINT8 Length
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SMBIOS_HANDLE_A72_L2,
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},
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3,
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0x181, //L2 enabled, WB
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512, //512k D-cache max
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512, //512k installed
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{0,1}, //SRAM type
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{0,1}, //SRAM type
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0, //speed unknown
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CacheErrorSingleBit, //ECC checking
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CacheTypeUnified, //instruction cache
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CacheAssociativity16Way, //16 way associative
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// SMBIOS 3.1.0 fields
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512, //512k D-cache max
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512, //512k installed
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};
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STATIC SMBIOS_TABLE_TYPE7 mArmadaDefaultType7_l3 = {
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{ // SMBIOS_STRUCTURE Hdr
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EFI_SMBIOS_TYPE_CACHE_INFORMATION, // UINT8 Type
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sizeof (SMBIOS_TABLE_TYPE7), // UINT8 Length
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SMBIOS_HANDLE_L3,
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},
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4,
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0x182, //L3 enabled, WB
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1024, //1M cache max
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1024, //1M installed
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{0,1}, //SRAM type
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{0,1}, //SRAM type
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0, //speed unknown
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CacheErrorSingleBit, //ECC checking
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CacheTypeUnified, //instruction cache
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CacheAssociativity8Way, //8 way associative
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// SMBIOS 3.1.0 fields
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1024, //1M cache max
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1024, //1M installed
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};
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STATIC CONST CHAR8 *mArmadaDefaultType7Strings[] = {
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"L1 Instruction\0", /* L1I */
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"L1 Data\0", /* L1D */
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"L2\0", /* L2 */
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"L3\0", /* L3 */
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NULL
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};
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// Slots
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STATIC SMBIOS_TABLE_TYPE9 mArmadaDefaultType9_0 = {
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{ // SMBIOS_STRUCTURE Hdr
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EFI_SMBIOS_TYPE_INACTIVE, // UINT8 Type
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sizeof (SMBIOS_TABLE_TYPE9), // UINT8 Length
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SMBIOS_HANDLE_PI_RESERVED,
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},
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1, // CP0 PCIE0
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SlotTypePciExpressGen2X1,
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SlotDataBusWidth1X,
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SlotUsageUnknown,
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SlotLengthShort,
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0,
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{1}, //Unknown
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{1,0,1}, //PME and SMBUS
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0,
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0,
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1,
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};
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STATIC SMBIOS_TABLE_TYPE9 mArmadaDefaultType9_1 = {
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{ // SMBIOS_STRUCTURE Hdr
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EFI_SMBIOS_TYPE_INACTIVE, // UINT8 Type
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sizeof (SMBIOS_TABLE_TYPE9), // UINT8 Length
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SMBIOS_HANDLE_PI_RESERVED,
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},
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2, // CP0 PCIE1
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SlotTypePciExpressGen2X1,
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SlotDataBusWidth1X,
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SlotUsageUnknown,
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SlotLengthShort,
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0,
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{1},
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{1,0,1}, //PME and SMBUS
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0,
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0,
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2,
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};
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STATIC SMBIOS_TABLE_TYPE9 mArmadaDefaultType9_2 = {
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{ // SMBIOS_STRUCTURE Hdr
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EFI_SMBIOS_TYPE_INACTIVE, // UINT8 Type
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sizeof (SMBIOS_TABLE_TYPE9), // UINT8 Length
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SMBIOS_HANDLE_PI_RESERVED,
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},
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3, // CP0 PCIE2
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SlotTypePciExpressGen2X1,
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SlotDataBusWidth1X,
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SlotUsageUnknown,
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SlotLengthShort,
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0,
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{1},
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{1,0,1}, //PME and SMBUS
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0,
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0,
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3,
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};
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STATIC SMBIOS_TABLE_TYPE9 mArmadaDefaultType9_3 = {
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{ // SMBIOS_STRUCTURE Hdr
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EFI_SMBIOS_TYPE_INACTIVE, // UINT8 Type
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sizeof (SMBIOS_TABLE_TYPE9), // UINT8 Length
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SMBIOS_HANDLE_PI_RESERVED,
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},
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4, // CP1 PCIE0
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SlotTypePciExpressGen2X1,
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SlotDataBusWidth1X,
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SlotUsageUnknown,
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SlotLengthShort,
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0,
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{1},
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{1,0,1}, //PME and SMBUS
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0,
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0,
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0xc,
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};
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STATIC SMBIOS_TABLE_TYPE9 mArmadaDefaultType9_4 = {
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{ // SMBIOS_STRUCTURE Hdr
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EFI_SMBIOS_TYPE_INACTIVE, // UINT8 Type
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sizeof (SMBIOS_TABLE_TYPE9), // UINT8 Length
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SMBIOS_HANDLE_PI_RESERVED,
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},
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5, // CP1 PCIE1
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SlotTypePciExpressGen2X1,
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SlotDataBusWidth1X,
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SlotUsageUnknown,
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SlotLengthShort,
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0,
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{1},
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{1,0,1}, //PME and SMBUS
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0,
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0,
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0xc,
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};
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STATIC SMBIOS_TABLE_TYPE9 mArmadaDefaultType9_5 = {
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{ // SMBIOS_STRUCTURE Hdr
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EFI_SMBIOS_TYPE_INACTIVE, // UINT8 Type
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sizeof (SMBIOS_TABLE_TYPE9), // UINT8 Length
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SMBIOS_HANDLE_PI_RESERVED,
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},
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6, // CP1 PCIE2
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SlotTypePciExpressGen2X1,
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SlotDataBusWidth1X,
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SlotUsageUnknown,
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SlotLengthShort,
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0,
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{1},
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{1,0,1}, //PME and SMBUS
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0,
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0,
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0xc,
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};
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STATIC CHAR8 CONST *mArmadaDefaultType9Strings[] = {
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"PCIE0 CP0 \0",/* Slot0 */
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"PCIE1 CP0 \0",/* Slot1 */
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"PCIE2 CP0 \0",/* Slot2 */
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"PCIE0 CP1 \0",/* Slot3 */
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"PCIE1 CP1 \0",/* Slot4 */
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"PCIE2 CP1 \0",/* Slot5 */
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NULL
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};
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// Memory array
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STATIC SMBIOS_TABLE_TYPE16 mArmadaDefaultType16 = {
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{ // SMBIOS_STRUCTURE Hdr
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EFI_SMBIOS_TYPE_PHYSICAL_MEMORY_ARRAY, // UINT8 Type
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sizeof (SMBIOS_TABLE_TYPE16), // UINT8 Length
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SMBIOS_HANDLE_MEMORY,
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},
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MemoryArrayLocationSystemBoard, //on motherboard
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MemoryArrayUseSystemMemory, //system RAM
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MemoryErrorCorrectionNone, //ECC RAM
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0x1000000, //16GB
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0xFFFE, //No error information structure
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0x1, //soldered memory
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};
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STATIC CHAR8 CONST *mArmadaDefaultType16Strings[] = {
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NULL
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};
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// Memory device
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STATIC SMBIOS_TABLE_TYPE17 mArmadaDefaultType17 = {
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{ // SMBIOS_STRUCTURE Hdr
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EFI_SMBIOS_TYPE_MEMORY_DEVICE, // UINT8 Type
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sizeof (SMBIOS_TABLE_TYPE17), // UINT8 Length
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SMBIOS_HANDLE_DIMM,
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},
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SMBIOS_HANDLE_MEMORY, //array to which this module belongs
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0xFFFE, //no errors
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64, //single DIMM, no ECC is 64bits (for ecc this would be 72)
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32, //data width of this device (32-bits)
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0, //Memory size obtained dynamically
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MemoryFormFactorRowOfChips, //Memory factor
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0, //Not part of a set
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1, //Location
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2, //Bank 0
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MemoryTypeDdr4, //DDR4
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{0,0,0,0,0,0,0,0,0,0,0,0,0,0,1}, //unbuffered
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0, //DRAM speed - requires update
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0, //varies between diffrent production runs
|
0, //serial
|
0, //asset tag
|
0, //part number
|
0, //rank
|
0, // ExtendedSize; (since Size < 32GB-1)
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0, // ConfiguredMemoryClockSpeed - initialized at runtime
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0, // MinimumVoltage; (unknown)
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0, // MaximumVoltage; (unknown)
|
0, // ConfiguredVoltage; (unknown)
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MemoryTechnologyDram, // MemoryTechnology
|
{{ // MemoryOperatingModeCapability
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0, // Reserved :1;
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0, // Other :1;
|
0, // Unknown :1;
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1, // VolatileMemory :1;
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0, // ByteAccessiblePersistentMemory :1;
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0, // BlockAccessiblePersistentMemory :1;
|
0 // Reserved :10;
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}},
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0, // FirwareVersion
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0, // ModuleManufacturerID (unknown)
|
0, // ModuleProductID (unknown)
|
0, // MemorySubsystemControllerManufacturerID (unknown)
|
0, // MemorySubsystemControllerProductID (unknown)
|
0, // NonVolatileSize
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0, // VolatileSize - initialized at runtime
|
0, // CacheSize
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0, // LogicalSize
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0, // ExtendedSpeed,
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0 // ExtendedConfiguredMemorySpeed
|
};
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STATIC CHAR8 CONST *mArmadaDefaultType17Strings[] = {
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"DIMM SLOT\0", /* location */
|
"BANK 0\0", /* bank description */
|
NULL
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};
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|
//
|
// Memory array mapped address, this structure
|
// is overridden by SmbiosInstallMemoryStructure.
|
//
|
STATIC SMBIOS_TABLE_TYPE19 mArmadaDefaultType19 = {
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{ // SMBIOS_STRUCTURE Hdr
|
EFI_SMBIOS_TYPE_MEMORY_ARRAY_MAPPED_ADDRESS, // UINT8 Type
|
sizeof (SMBIOS_TABLE_TYPE19), // UINT8 Length
|
SMBIOS_HANDLE_PI_RESERVED,
|
},
|
0xFFFFFFFF, //invalid, look at extended addr field
|
0xFFFFFFFF,
|
SMBIOS_HANDLE_DIMM, //handle
|
1,
|
0x080000000, //starting addr of first 2GB
|
0x100000000, //ending addr of first 2GB
|
};
|
|
// System boot infomArmadaDefaultType4.
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STATIC SMBIOS_TABLE_TYPE32 mArmadaDefaultType32 = {
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{ // SMBIOS_STRUCTURE Hdr
|
EFI_SMBIOS_TYPE_SYSTEM_BOOT_INFORMATION, // UINT8 Type
|
sizeof (SMBIOS_TABLE_TYPE32), // UINT8 Length
|
SMBIOS_HANDLE_PI_RESERVED,
|
},
|
{0, 0, 0, 0, 0, 0}, //reserved
|
BootInformationStatusNoError,
|
};
|
|
STATIC CHAR8 CONST *mArmadaDefaultType32Strings[] = {
|
NULL
|
};
|
|
STATIC CONST VOID *DefaultCommonTables[][2] =
|
{
|
{ &mArmadaDefaultType0, mArmadaDefaultType0Strings },
|
{ &mArmadaDefaultType1, mArmadaDefaultType1Strings },
|
{ &mArmadaDefaultType2, mArmadaDefaultType2Strings },
|
{ &mArmadaDefaultType3, mArmadaDefaultType3Strings },
|
{ &mArmadaDefaultType4, mArmadaDefaultType4Strings },
|
{ &mArmadaDefaultType7_a72_l1i, mArmadaDefaultType7Strings },
|
{ &mArmadaDefaultType7_a72_l1d, mArmadaDefaultType7Strings },
|
{ &mArmadaDefaultType7_a72_l2, mArmadaDefaultType7Strings },
|
{ &mArmadaDefaultType7_l3, mArmadaDefaultType7Strings },
|
{ &mArmadaDefaultType9_0, mArmadaDefaultType9Strings },
|
{ &mArmadaDefaultType9_1, mArmadaDefaultType9Strings },
|
{ &mArmadaDefaultType9_2, mArmadaDefaultType9Strings },
|
{ &mArmadaDefaultType9_3, mArmadaDefaultType9Strings },
|
{ &mArmadaDefaultType9_4, mArmadaDefaultType9Strings },
|
{ &mArmadaDefaultType9_5, mArmadaDefaultType9Strings },
|
{ &mArmadaDefaultType16, mArmadaDefaultType16Strings },
|
{ &mArmadaDefaultType17, mArmadaDefaultType17Strings },
|
{ &mArmadaDefaultType32, mArmadaDefaultType32Strings },
|
{ NULL, NULL },
|
};
|
|
/**
|
|
Create SMBIOS record.
|
|
Converts a fixed SMBIOS structure and an array of pointers to strings into
|
an SMBIOS record where the strings are cat'ed on the end of the fixed record
|
and terminated via a double NULL and add to SMBIOS table.
|
|
SMBIOS_TABLE_TYPE32 gSmbiosType12 = {
|
{ EFI_SMBIOS_TYPE_SYSTEM_CONFIGURATION_OPTIONS, sizeof (SMBIOS_TABLE_TYPE12), 0 },
|
1 // StringCount
|
};
|
|
CHAR8 *gSmbiosType12Strings[] = {
|
"Not Found",
|
NULL
|
};
|
|
...
|
|
LogSmbiosData (
|
(EFI_SMBIOS_TABLE_HEADER*)&gSmbiosType12,
|
gSmbiosType12Strings
|
);
|
|
@param Smbios SMBIOS protocol
|
@param Template Fixed SMBIOS structure, required.
|
@param StringArray Array of strings to convert to an SMBIOS string pack.
|
NULL is OK.
|
**/
|
STATIC
|
EFI_STATUS
|
EFIAPI
|
LogSmbiosData (
|
IN EFI_SMBIOS_PROTOCOL *Smbios,
|
IN EFI_SMBIOS_TABLE_HEADER *Template,
|
IN CONST CHAR8 * CONST *StringArray
|
)
|
{
|
EFI_STATUS Status;
|
EFI_SMBIOS_TABLE_HEADER *Record;
|
UINTN Index;
|
UINTN StringSize;
|
UINTN Size;
|
CHAR8 *Str;
|
|
|
// Calculate the size of the fixed record and optional string pack
|
Size = Template->Length;
|
if (StringArray == NULL) {
|
// At least a double null is required
|
Size += 1;
|
} else {
|
for (Index = 0; StringArray[Index] != NULL; Index++) {
|
StringSize = AsciiStrSize (StringArray[Index]);
|
Size += StringSize;
|
}
|
if (StringArray[0] == NULL) {
|
// At least a double null is required
|
Size += 1;
|
}
|
|
// Don't forget the terminating double null
|
Size += 1;
|
}
|
|
// Copy over Template
|
Record = (EFI_SMBIOS_TABLE_HEADER *)AllocateZeroPool (Size);
|
if (Record == NULL) {
|
return EFI_OUT_OF_RESOURCES;
|
}
|
CopyMem (Record, Template, Template->Length);
|
|
// Append string pack
|
Str = (CHAR8*)((UINTN)Record + Record->Length);
|
for (Index = 0; StringArray[Index] != NULL; Index++) {
|
StringSize = AsciiStrSize (StringArray[Index]);
|
CopyMem (Str, StringArray[Index], StringSize);
|
Str += StringSize;
|
}
|
*Str = 0;
|
|
Status = Smbios->Add (Smbios,
|
NULL,
|
&Record->Handle,
|
Record);
|
ASSERT_EFI_ERROR (Status);
|
|
FreePool (Record);
|
|
return Status;
|
}
|
|
/**
|
Installs a memory descriptor (type19) for the given address range
|
|
@param Smbios SMBIOS protocol.
|
@param StartingAddress Start address of the memory chunk.
|
@param RegionLength Memory chunk size.
|
|
**/
|
EFI_STATUS
|
SmbiosInstallMemoryStructure (
|
IN EFI_SMBIOS_PROTOCOL *Smbios,
|
IN UINT64 StartingAddress,
|
IN UINT64 RegionLength
|
)
|
{
|
EFI_SMBIOS_HANDLE SmbiosHandle;
|
SMBIOS_TABLE_TYPE19 MemoryDescriptor;
|
EFI_STATUS Status = EFI_SUCCESS;
|
|
CopyMem (&MemoryDescriptor,
|
&mArmadaDefaultType19,
|
sizeof (SMBIOS_TABLE_TYPE19));
|
|
MemoryDescriptor.ExtendedStartingAddress = StartingAddress;
|
MemoryDescriptor.ExtendedEndingAddress = StartingAddress + RegionLength;
|
SmbiosHandle = MemoryDescriptor.Hdr.Handle;
|
|
Status = Smbios->Add (Smbios,
|
NULL,
|
&SmbiosHandle,
|
(EFI_SMBIOS_TABLE_HEADER*) &MemoryDescriptor);
|
|
return Status;
|
}
|
|
/**
|
Install a whole table worth of structructures
|
|
@param Smbios SMBIOS protocol.
|
@param DefaultTables A pointer to the default SMBIOS table structure.
|
|
**/
|
EFI_STATUS
|
SmbiosInstallStructures (
|
IN EFI_SMBIOS_PROTOCOL *Smbios,
|
IN CONST VOID *DefaultTables[][2]
|
)
|
{
|
EFI_STATUS Status = EFI_SUCCESS;
|
INTN TableEntry;
|
|
for (TableEntry = 0; DefaultTables[TableEntry][0] != NULL; TableEntry++) {
|
// Omit disabled tables
|
if (((EFI_SMBIOS_TABLE_HEADER *)DefaultTables[TableEntry][0])->Type ==
|
EFI_SMBIOS_TYPE_INACTIVE) {
|
continue;
|
}
|
|
Status = LogSmbiosData (Smbios,
|
((EFI_SMBIOS_TABLE_HEADER *)DefaultTables[TableEntry][0]),
|
DefaultTables[TableEntry][1]);
|
if (EFI_ERROR (Status))
|
break;
|
}
|
|
return Status;
|
}
|
|
/**
|
Update memory information basing on the HOB list.
|
|
@param Smbios SMBIOS protocol
|
|
**/
|
STATIC
|
EFI_STATUS
|
SmbiosMemoryInstall (
|
IN EFI_SMBIOS_PROTOCOL *Smbios
|
)
|
{
|
EFI_PEI_HOB_POINTERS Hob;
|
UINT64 MemorySize;
|
EFI_STATUS Status;
|
|
MemorySize = 0;
|
|
//
|
// Get the HOB list for processing
|
//
|
Hob.Raw = GetHobList ();
|
|
//
|
// Collect memory ranges
|
//
|
while (!END_OF_HOB_LIST (Hob)) {
|
if (Hob.Header->HobType == EFI_HOB_TYPE_RESOURCE_DESCRIPTOR) {
|
if (Hob.ResourceDescriptor->ResourceType == EFI_RESOURCE_SYSTEM_MEMORY) {
|
MemorySize += (UINT64)(Hob.ResourceDescriptor->ResourceLength);
|
|
Status = SmbiosInstallMemoryStructure (Smbios,
|
Hob.ResourceDescriptor->PhysicalStart,
|
Hob.ResourceDescriptor->ResourceLength);
|
if (EFI_ERROR(Status)) {
|
return Status;
|
}
|
}
|
}
|
Hob.Raw = GET_NEXT_HOB (Hob);
|
}
|
|
//
|
// Update TYPE17 memory size fields
|
//
|
mArmadaDefaultType17.Size = (UINT16)(MemorySize >> 20);
|
mArmadaDefaultType17.VolatileSize = MemorySize;
|
|
return EFI_SUCCESS;
|
}
|
|
/**
|
Install all structures from the DefaultTables structure
|
|
@param Smbios SMBIOS protocol
|
|
**/
|
EFI_STATUS
|
SmbiosInstallAllStructures (
|
IN EFI_SMBIOS_PROTOCOL *Smbios
|
)
|
{
|
EFI_STATUS Status;
|
UINT32 FirmwareMajorRevisionNumber;
|
UINT32 FirmwareMinorRevisionNumber;
|
|
FirmwareMajorRevisionNumber = (PcdGet32 (PcdFirmwareRevision) >> 16) & 0xFF;
|
FirmwareMinorRevisionNumber = PcdGet32 (PcdFirmwareRevision) & 0xFF;
|
|
//
|
// Update Firmware Revision, CPU and DRAM frequencies.
|
//
|
mArmadaDefaultType0.SystemBiosMajorRelease = FirmwareMajorRevisionNumber;
|
mArmadaDefaultType0.SystemBiosMinorRelease = FirmwareMinorRevisionNumber;
|
mArmadaDefaultType4.CurrentSpeed = SampleAtResetGetCpuFrequency ();
|
mArmadaDefaultType17.Speed = SampleAtResetGetDramFrequency ();
|
mArmadaDefaultType17.ConfiguredMemoryClockSpeed = SampleAtResetGetDramFrequency ();
|
|
//
|
// Generate memory descriptors.
|
//
|
Status = SmbiosMemoryInstall (Smbios);
|
ASSERT_EFI_ERROR (Status);
|
|
//
|
// Install all tables.
|
//
|
Status = SmbiosInstallStructures (Smbios, DefaultCommonTables);
|
ASSERT_EFI_ERROR (Status);
|
|
return EFI_SUCCESS;
|
}
|
|
/**
|
Installs SMBIOS information for Armada platforms
|
|
@param ImageHandle Module's image handle
|
@param SystemTable Pointer of EFI_SYSTEM_TABLE
|
|
@retval EFI_SUCCESS Smbios data successfully installed
|
@retval Other Smbios data was not installed
|
|
**/
|
EFI_STATUS
|
EFIAPI
|
SmbiosPlatformDriverEntryPoint (
|
IN EFI_HANDLE ImageHandle,
|
IN EFI_SYSTEM_TABLE *SystemTable
|
)
|
{
|
EFI_STATUS Status;
|
EFI_SMBIOS_PROTOCOL *Smbios;
|
|
//
|
// Find the SMBIOS protocol
|
//
|
Status = gBS->LocateProtocol (&gEfiSmbiosProtocolGuid,
|
NULL,
|
(VOID **)&Smbios);
|
if (EFI_ERROR (Status)) {
|
return Status;
|
}
|
|
Status = SmbiosInstallAllStructures (Smbios);
|
|
return Status;
|
}
|
