/** @file
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@copyright
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Copyright 2006 - 2021 Intel Corporation. <BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef _mem_defaults_h
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#define _mem_defaults_h
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//
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// SMBUS Clk Period default set by PcdMrcSmbusSpeedDefault
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//
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#define SMB_CLK_100K 0
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#define SMB_CLK_400K 1
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#define SMB_CLK_700K 2
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#define SMB_CLK_1M 3
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#define MAX_PARTIAL_MIRROR 4 //Maximum number of partial mirror regions that can be created
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//
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// Limit of channels to be tested by AdvMemTest
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//
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#define ADV_MT_LIST_LIMIT 8
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#define ADV_MT_EMPTY_MASK 0xFFFFFFFF
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#endif // _mem_defaults_h
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