/** @file
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Unified Silicon Register Access Types
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@copyright
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Copyright 2011 - 2021 Intel Corporation. <BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef __USRA_ACCESS_TYPE_H__
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#define __USRA_ACCESS_TYPE_H__
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typedef enum {
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AddrTypePCIE = 0,
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AddrTypePCIEBLK,
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AddrTypeCSR,
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AddrTypePCIIO,
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AddrTypeCSRMEM,
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AddrTypeCSRCFG,
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AddrTypeMaximum
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} USRA_ADDR_TYPE;
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typedef enum {
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CsrBoxInst = 0,
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CsrMcId,
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CsrChId,
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CsrIoId,
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InstTypeMax
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} CSR_INSTANCE_TYPE;
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typedef enum {
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UsraWidth8 = 0,
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UsraWidth16,
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UsraWidth32,
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UsraWidth64,
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UsraWidthFifo8,
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UsraWidthFifo16,
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UsraWidthFifo32,
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UsraWidthFifo64,
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UsraWidthFill8,
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UsraWidthFill16,
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UsraWidthFill32,
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UsraWidthFill64,
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UsraWidthMaximum
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} USRA_ACCESS_WIDTH;
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#define USRA_ENABLE 1;
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#define USRA_DISABLE 0;
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#define PCI_CONFIGURATION_ADDRESS_PORT 0xCF8
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#define PCI_CONFIGURATION_DATA_PORT 0xCFC
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#pragma pack (1)
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typedef struct {
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UINT32 RawData32[2]; // RawData of two UINT32 type, place holder
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UINT32 AddrType:8; // Address type: CSR, PCIE, MMIO, IO, SMBus ...
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UINT32 AccessWidth:4; // The Access width for 8, 16,32,64 -bit access
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UINT32 FastBootEn:1; // Fast Boot Flag, can be used to log register access trace for fast boot
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UINT32 S3Enable:1; // S3 Enable bit, when enabled, it will save the write to script to support S3
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UINT32 HptrType:1; // Host Pointer type, below or above 4GB
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UINT32 ConvertedType:1; // The address type was from converted type, use this field for address migration support
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UINT32 RFU3:16; // Reserved for User use or Future Use
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UINT32 HostPtr:32; // The Host Pointer, to point to Attribute buffer etc.
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} ADDR_ATTRIBUTE_TYPE;
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typedef struct {
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UINT32 Offset:12; // The PCIE Register Offset
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UINT32 Func:3; // The PCIE Function
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UINT32 Dev:5; // The PCIE Device
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UINT32 Bus:8; // The PCIE Bus
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UINT32 RFU1:4; // Reserved for User use or Future Use
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UINT32 Seg:16; // The PCI Segment
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UINT32 Count:16; // Access Count
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} USRA_PCIE_ADDR_TYPE;
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#define BUS_DEV_FUN_OFFSET_MASK 0x0FFFFFFF
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typedef struct {
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UINT32 Offset; // This Offset occupies 32 bits. It's platform code's responsibilty to define the meaning of specific
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// bits and use them accordingly.
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UINT32 InstId:8; // The Box Instance, 0 based, Index/Port within the box, Set Index as 0 if the box has only one instances
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UINT32 SocketId:8; // The Socket Id
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UINT32 InstType:8; // The Instance Type
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UINT32 RFU:8; // Reserved for User use or Future Ues
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} USRA_CSR_ADDR_TYPE;
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typedef struct {
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UINT32 Offset:8; // The PCIIO Register Offset
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UINT32 Func:3; // The PCIIO Function
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UINT32 Dev:5; // The PCIIO Device
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UINT32 Bus:8; // The PCIIO Bus
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UINT32 RFU:7; // Reserved for User use or Future Use
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UINT32 EnableBit:1; // The PCIIO Register Enable Bit
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} USRA_PCIIO_ADDR_TYPE;
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typedef struct {
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UINT32 Offset:32; // The register offset
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UINT32 SocketId:8; // The socket ID
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UINT32 MemBarId:8; // The ID of the BAR
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UINT32 High64Split:1; // Move address up to access top of 64 bit register
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UINT32 Reserved:15; // Reserved for User use or Future Use
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} USRA_CSR_MEM_ADDR_TYPE;
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typedef struct {
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UINT32 Offset:32; // The register offset
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UINT32 SocketId:7; // The socket ID
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UINT32 Bus:8; // Bus
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UINT32 Device:8; // Device
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UINT32 Function:8; // Function
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UINT32 High64Split:1; // Move address up to access top of 64 bit register
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} USRA_CSR_CFG_ADDR_TYPE;
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#pragma pack()
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typedef union {
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UINT32 dwRawData[4];
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ADDR_ATTRIBUTE_TYPE Attribute; // The address attribute type.
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USRA_PCIE_ADDR_TYPE Pcie;
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USRA_PCIE_ADDR_TYPE PcieBlk;
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USRA_CSR_ADDR_TYPE Csr;
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USRA_PCIIO_ADDR_TYPE PciIo;
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USRA_CSR_MEM_ADDR_TYPE CsrMem;
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USRA_CSR_CFG_ADDR_TYPE CsrCfg;
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} USRA_ADDRESS;
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//
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// Assemble macro for USRA_PCIE_ADDR_TYPE
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//
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#define USRA_PCIE_SEG_ADDRESS(Address, WIDTH, SEG, BUS, DEV, FUNC, OFFSET) \
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USRA_ZERO_ADDRESS(Address); \
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((USRA_ADDRESS *)(&Address))->Attribute.AccessWidth = WIDTH; \
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((USRA_ADDRESS *)(&Address))->Attribute.AddrType = AddrTypePCIE; \
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((USRA_ADDRESS *)(&Address))->Pcie.Seg = (UINT32)(SEG); \
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((USRA_ADDRESS *)(&Address))->Pcie.Bus = (UINT32)(BUS) & 0xFF; \
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((USRA_ADDRESS *)(&Address))->Pcie.Dev = (UINT32)(DEV) & 0x1F; \
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((USRA_ADDRESS *)(&Address))->Pcie.Func = (UINT32)(FUNC) & 0x07; \
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((USRA_ADDRESS *)(&Address))->Pcie.Offset = (UINT32)(OFFSET) & 0x0FFF
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//
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// Assemble macro for USRA_BDFO_ADDR_TYPE
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//
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#define USRA_PCIE_SEG_BDFO_ADDRESS(Address, WIDTH, SEG, BDFO) \
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USRA_ZERO_ADDRESS(Address); \
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((USRA_ADDRESS *)(&Address))->Attribute.AccessWidth = WIDTH; \
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((USRA_ADDRESS *)(&Address))->Attribute.AddrType = AddrTypePCIE; \
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((USRA_ADDRESS *)(&Address))->Pcie.Seg = (UINT32)(SEG); \
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((USRA_ADDRESS *)(&Address))->Pcie.Bus = (UINT32)(BDFO >> 20) & 0xFF; \
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((USRA_ADDRESS *)(&Address))->Pcie.Dev = (UINT32)(BDFO >> 15) & 0x1F; \
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((USRA_ADDRESS *)(&Address))->Pcie.Func = (UINT32)(BDFO >> 12) & 0x07; \
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((USRA_ADDRESS *)(&Address))->Pcie.Offset = (UINT32)(BDFO) & 0x0FFF
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//
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// Assemble macro for USRA_PCIE_SEG_LIB_ADDR_TYPE
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//
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#define USRA_PCIE_SEG_LIB_ADDRESS(Address, PCISEGADDR, WIDTH) \
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USRA_ZERO_ADDRESS(Address); \
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((USRA_ADDRESS *)(&Address))->Attribute.AccessWidth = WIDTH; \
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((USRA_ADDRESS *)(&Address))->Attribute.AddrType = AddrTypePCIE; \
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((USRA_ADDRESS *)(&Address))->Pcie.Seg = (UINT32)((PCISEGADDR >> 32) & 0x0000FFFF); \
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((USRA_ADDRESS *)(&Address))->Attribute.RawData32[0] = (UINT32)(PCISEGADDR & BUS_DEV_FUN_OFFSET_MASK)
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//
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// Assemble macro for USRA_PCIE_BLK_ADDR_TYPE
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//
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#define USRA_BLOCK_PCIE_ADDRESS(Address, WIDTH, COUNT, SEG, BUS, DEV, FUNC, OFFSET) \
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USRA_ZERO_ADDRESS(Address); \
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((USRA_ADDRESS *)(&Address))->Attribute.AccessWidth = WIDTH; \
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((USRA_ADDRESS *)(&Address))->Attribute.AddrType = AddrTypePCIEBLK; \
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((USRA_ADDRESS *)(&Address))->PcieBlk.Count = (UINT32)COUNT; \
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((USRA_ADDRESS *)(&Address))->PcieBlk.Seg = (UINT32)SEG; \
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((USRA_ADDRESS *)(&Address))->PcieBlk.Bus = (UINT32)(BUS) & 0xFF; \
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((USRA_ADDRESS *)(&Address))->PcieBlk.Dev = (UINT32)(DEV) & 0x1F; \
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((USRA_ADDRESS *)(&Address))->PcieBlk.Func = (UINT32)(FUNC) & 0x07; \
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((USRA_ADDRESS *)(&Address))->PcieBlk.Offset = (UINT32)(OFFSET) & 0x0FFF
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//
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// Assemble macro for USRA_PCIE_SEG_ADDR_TYPE
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//
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#define USRA_PCIE_ADDRESS(Address, WIDTH, BUS, DEV, FUNC, OFFSET) \
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USRA_PCIE_SEG_ADDRESS(Address, WIDTH, 0, BUS, DEV, FUNC, OFFSET)
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//
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// Assemble macro for USRA CSR common Address
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//
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#define USRA_CSR_COMMON_ADDRESS(Address, SOCKETID, INSTID, CSROFFSET) \
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USRA_ZERO_ADDRESS(Address); \
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((USRA_ADDRESS *)(&Address))->Csr.SocketId = SOCKETID; \
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((USRA_ADDRESS *)(&Address))->Csr.InstId = INSTID; \
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((USRA_ADDRESS *)(&Address))->Csr.Offset = CSROFFSET
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//
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// Assemble macro for address type CSR
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//
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#define USRA_CSR_OFFSET_ADDRESS(Address, SOCKETID, INSTID, CSROFFSET) \
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USRA_CSR_COMMON_ADDRESS(Address, SOCKETID, INSTID, CSROFFSET); \
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((USRA_ADDRESS *)(&Address))->Csr.InstType = CsrBoxInst; \
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((USRA_ADDRESS *)(&Address))->Attribute.AddrType = AddrTypeCSR
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#define USRA_CSR_MCID_OFFSET_ADDRESS(Address, SOCKETID, INSTID, CSROFFSET) \
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USRA_CSR_COMMON_ADDRESS(Address, SOCKETID, INSTID, CSROFFSET); \
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((USRA_ADDRESS *)(&Address))->Csr.InstType = CsrMcId; \
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((USRA_ADDRESS *)(&Address))->Attribute.AddrType = AddrTypeCSR
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#define USRA_CSR_CHID_OFFSET_ADDRESS(Address, SOCKETID, INSTID, CSROFFSET) \
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USRA_CSR_COMMON_ADDRESS(Address, SOCKETID, INSTID, CSROFFSET); \
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((USRA_ADDRESS *)(&Address))->Csr.InstType = CsrChId; \
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((USRA_ADDRESS *)(&Address))->Attribute.AddrType = AddrTypeCSR
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#define USRA_CSR_IOID_OFFSET_ADDRESS(Address, SOCKETID, INSTID, CSROFFSET) \
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USRA_CSR_COMMON_ADDRESS(Address, SOCKETID, INSTID, CSROFFSET); \
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((USRA_ADDRESS *)(&Address))->Csr.InstType = CsrIoId; \
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((USRA_ADDRESS *)(&Address))->Attribute.AddrType = AddrTypeCSR
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//
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// Assemble macro for USRA_PCIIO_ADDR_TYPE
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//
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#define USRA_PCI_IO_ADDRESS(Address, WIDTH, BUS, DEV, FUNC, OFFSET) \
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USRA_ZERO_ADDRESS(Address); \
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((USRA_ADDRESS *)(&Address))->Attribute.AccessWidth = WIDTH; \
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((USRA_ADDRESS *)(&Address))->Attribute.AddrType = AddrTypePCIIO; \
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((USRA_ADDRESS *)(&Address))->PciIo.Bus = (UINT32)(BUS) & 0xFF; \
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((USRA_ADDRESS *)(&Address))->PciIo.Dev = (UINT32)(DEV) & 0x1F; \
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((USRA_ADDRESS *)(&Address))->PciIo.Func = (UINT32)(FUNC) & 0x07; \
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((USRA_ADDRESS *)(&Address))->PciIo.Offset = (UINT32)(OFFSET) & 0xFF; \
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((USRA_ADDRESS *)(&Address))->PciIo.EnableBit = 1
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//
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// Assemble macro for USRA_BDFO_PCIIO_ADDR_TYPE
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//
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#define USRA_PCI_IO_BDFO_ADDRESS(Address, WIDTH, BDFO) \
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USRA_ZERO_ADDRESS(Address); \
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((USRA_ADDRESS *)(&Address))->Attribute.AccessWidth = WIDTH; \
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((USRA_ADDRESS *)(&Address))->Attribute.AddrType = AddrTypePCIIO; \
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((USRA_ADDRESS *)(&Address))->Attribute.RawData32[0] = (UINT32)(BDFO) & 0xFFFFFF; \
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((USRA_ADDRESS *)(&Address))->PciIo.EnableBit = 1
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//
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// Assemble macro for USRA_CSR_MMIO_ADDR_TYPE
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//
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#define USRA_CSR_MEM_ADDRESS(Address, SOCKETID, MEMBARID, OFFSET, WIDTH) \
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USRA_ZERO_ADDRESS(Address); \
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((USRA_ADDRESS *)(&Address))->Attribute.AddrType = AddrTypeCSRMEM; \
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((USRA_ADDRESS *)(&Address))->Attribute.AccessWidth = WIDTH; \
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((USRA_ADDRESS *)(&Address))->CsrMem.SocketId = SOCKETID; \
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((USRA_ADDRESS *)(&Address))->CsrMem.MemBarId = MEMBARID; \
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((USRA_ADDRESS *)(&Address))->CsrMem.Offset = OFFSET; \
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((USRA_ADDRESS *)(&Address))->CsrMem.High64Split = 0;
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//
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// Assemble macro for USRA_CSR_CFG_ADDR_TYPE
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//
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#define USRA_CSR_CFG_ADDRESS(Address, SOCKETID, BUS, DEVICE, FUNCTION, OFFSET, WIDTH) \
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USRA_ZERO_ADDRESS(Address); \
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((USRA_ADDRESS *)(&Address))->Attribute.AddrType = AddrTypeCSRCFG; \
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((USRA_ADDRESS *)(&Address))->Attribute.AccessWidth = WIDTH; \
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((USRA_ADDRESS *)(&Address))->CsrCfg.SocketId = SOCKETID; \
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((USRA_ADDRESS *)(&Address))->CsrCfg.Bus = BUS; \
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((USRA_ADDRESS *)(&Address))->CsrCfg.Device = DEVICE; \
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((USRA_ADDRESS *)(&Address))->CsrCfg.Function = Function; \
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((USRA_ADDRESS *)(&Address))->CsrCfg.Offset = OFFSET; \
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((USRA_ADDRESS *)(&Address))->CsrCfg.High64Split = 0;
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//
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// Assemble macro for ZERO_USRA ADDRESS
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//
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#define USRA_ZERO_ADDRESS(Address) \
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((UINT32 *)&Address)[3] = (UINT32)0; \
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((UINT32 *)&Address)[2] = (UINT32)0; \
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((UINT32 *)&Address)[1] = (UINT32)0; \
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((UINT32 *)&Address)[0] = (UINT32)0
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//
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// Assemble macro for ZERO_ADDR_TYPE
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//
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#define USRA_ZERO_ADDRESS_TYPE(Address, AddressType) \
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((UINT32 *)&Address)[3] = (UINT32)0; \
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((UINT32 *)&Address)[2] = (UINT32)((AddressType) & 0x0FF); \
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((UINT32 *)&Address)[1] = (UINT32)0; \
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((UINT32 *)&Address)[0] = (UINT32)0
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#define USRA_ADDRESS_COPY(DestAddrPtr, SourceAddrPtr) \
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((UINT32 *)DestAddrPtr)[3] = ((UINT32 *)SourceAddrPtr)[3]; \
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((UINT32 *)DestAddrPtr)[2] = ((UINT32 *)SourceAddrPtr)[2]; \
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((UINT32 *)DestAddrPtr)[1] = ((UINT32 *)SourceAddrPtr)[1]; \
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((UINT32 *)DestAddrPtr)[0] = ((UINT32 *)SourceAddrPtr)[0];
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#endif
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