/** @file
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@copyright
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Copyright 2004 - 2021 Intel Corporation. <BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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// Definition Flag:
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// 1. KTI_SW_SIMULATION -> run with KTIRC Simulation
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// 2. IA32 -> run with IA32 mode
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#ifndef _KTI_HOST_H_
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#define _KTI_HOST_H_
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#include "DataTypes.h"
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#include "PlatformHost.h"
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#include <Upi/KtiSi.h>
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#include <Upi/KtiDisc.h>
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#include "MemHostChipCommon.h"
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#pragma pack(1)
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/*********************************************************
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KTIRC Host Structure Related
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*********************************************************/
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typedef enum {
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KTI_LINK0 = 0x0,
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KTI_LINK1,
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KTI_LINK2,
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KTI_LINK3,
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KTI_LINK4,
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KTI_LINK5
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} KTI_LOGIC_LINK;
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typedef struct {
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UINT8 Reserved1;
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UINT8 Reserved2;
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UINT8 Reserved3;
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UINT8 Reserved4;
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UINT8 Reserved5;
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UINT8 Reserved6;
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UINT8 Reserved7;
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UINT8 Reserved8;
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UINT8 Reserved9;
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UINT8 Reserved10;
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UINT8 Reserved11;
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UINT8 Reserved12;
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UINT8 Reserved13;
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UINT8 Reserved14;
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UINT8 Reserved15;
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UINT8 Reserved16;
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UINT8 Reserved17;
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UINT8 Reserved18;
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UINT8 Reserved19;
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UINT8 Reserved20;
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UINT8 Reserved21;
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UINT8 Reserved22;
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UINT8 Reserved23;
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UINT8 Reserved24;
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UINT8 Reserved25;
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UINT8 Reserved26;
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UINT8 Reserved27;
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UINT8 Reserved28;
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UINT8 Reserved29;
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UINT8 Reserved30;
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UINT8 Reserved31;
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UINT8 Reserved32;
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UINT8 Reserved33;
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UINT8 Reserved34;
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UINT8 Reserved35;
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UINT8 Reserved36;
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UINT8 Reserved37;
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UINT32 Reserved38;
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UINT8 Reserved39;
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UINT8 Reserved40;
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} KTI_RESERVED_3;
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typedef struct {
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UINT32 Reserved1:2;
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UINT32 Reserved2:2;
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UINT32 Reserved3:2;
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UINT32 Rsvd1 : 26;
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} KTI_RESERVED_1;
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typedef struct {
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UINT8 Reserved4 : 2;
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UINT8 Rsvd1 : 6;
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} KTI_RESERVED_2;
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typedef struct {
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KTI_RESERVED_1 Link[MAX_FW_KTI_PORTS];
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KTI_RESERVED_2 Phy[MAX_FW_KTI_PORTS];
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} KTI_RESERVED_4;
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/**
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Per Lane PHY Configuration
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These PHY settings are system dependent. Every socket/link/freq requires an instance of this structure.
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**/
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typedef struct {
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UINT8 SocketID; ///< Socket ID
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UINT8 AllLanesUseSameTxeq; ///< Use same TXEQ on all lanes
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UINT8 Freq; ///< The Link Speed these TXEQ settings should be used for
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UINT32 Link; ///< Port Number
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UINT32 TXEQL[20]; ///< TXEQ Settings
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UINT32 CTLEPEAK[5]; ///< CTLE Peaking Settings
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} PER_LANE_EPARAM_LINK_INFO;
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/**
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All Lanes PHY Configuration
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This is for full speed mode, all lanes have the same TXEQ setting
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**/
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typedef struct {
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UINT8 SocketID; ///< Socket ID
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UINT8 Freq; ///< The Link Speed these TXEQ settings should be used for
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UINT32 Link; ///< Port Number
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UINT32 AllLanesTXEQ; ///< TXEQ Setting
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UINT8 CTLEPEAK; ///< CTLE Peaking Setting
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} ALL_LANES_EPARAM_LINK_INFO;
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#define ADAPTIVE_CTLE 0x3f
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typedef enum {
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TYPE_UBOX = 0,
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TYPE_UBOX_IIO,
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TYPE_MCP,
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TYPE_FPGA,
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TYPE_HFI,
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TYPE_NAC,
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TYPE_GRAPHICS,
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TYPE_DINO,
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TYPE_RESERVED,
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TYPE_DISABLED, // This item must be prior to stack specific disable types
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TYPE_UBOX_IIO_DIS,
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TYPE_MCP_DIS,
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TYPE_FPGA_DIS,
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TYPE_HFI_DIS,
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TYPE_NAC_DIS,
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TYPE_GRAPHICS_DIS,
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TYPE_DINO_DIS,
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TYPE_RESERVED_DIS,
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TYPE_NONE
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} STACK_TYPE;
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//
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// Link layer settings, per link
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//
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typedef struct {
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UINT8 KtiPortDisable:1; // TRUE - Port disabled; FALSE- Port enabled (default)
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UINT8 KtiLinkVnaOverride:7; // Numeric value 0x00-0x7f
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UINT8 Rsvd:8;
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} KTI_CPU_LINK_SETTING;
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//
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// Phy general setting, per link
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//
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typedef struct {
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UINT32 KtiLinkSpeed:3;
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UINT32 Rsvd:29;
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} KTI_CPU_PHY_SETTING;
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//
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// Per CPU setting
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//
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typedef struct {
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KTI_CPU_LINK_SETTING Link[MAX_FW_KTI_PORTS];
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KTI_CPU_PHY_SETTING Phy[MAX_FW_KTI_PORTS];
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} KTI_CPU_SETTING;
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/**
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KTIRC input structure
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**/
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typedef struct {
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//
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// Protocol layer and other general options; note that "Auto" is provided only options whose value will change depending
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// on the topology, not for all options.
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//
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/**
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Indicates the ratio of Bus/MMIOL/IO resource to be allocated for each CPU's IIO.
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Value 0 indicates, that CPU is not relevant for the system. If resource is
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requested for an CPU that is not currently populated, KTIRC will assume
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that the ratio is 0 for that CPU and won't allocate any resources for it.
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If resource is not requested for a CPU that is populated, KTIRC will force
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the ratio for that CPU to 1.
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**/
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UINT8 BusRatio[MAX_SOCKET];
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UINT8 D2KCreditConfig; ///< 1 - Min, 2 - Med (Default), 3- Max
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UINT8 SnoopThrottleConfig; ///< 0 - Disabled (Default), 1 - Min, 2 - Med, 3- Max
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UINT8 SnoopAllCores; ///< 0 - Disabled, 1 - Enabled, 2 - Auto
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UINT8 LegacyVgaSoc; ///< Socket that claims the legacy VGA range; valid values are 0-7; 0 is default.
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UINT8 LegacyVgaStack; ///< Stack that claims the legacy VGA range; valid values are 0-3; 0 is default.
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UINT8 ColdResetRequestStart; ///< @deprecated Reserved.
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UINT8 P2pRelaxedOrdering; ///< 0 - Disable(default) 1 - Enable
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UINT8 DebugPrintLevel; ///< Bit 0 - Fatal, Bit1 - Warning, Bit2 - Info Summary; Bit 3 - Info detailed. 1 - Enable; 0 - Disable
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UINT8 SncEn; ///< 0 - Disable, (default) 1 - Enable
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UINT8 UmaClustering; ///< 0 - Disable, 2 - 2Clusters UMA, 4 - 4Clusters UMA
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UINT8 IoDcMode; ///< 0 - Disable IODC, 1 - AUTO (default), 2 - IODC_EN_REM_INVITOM_PUSH, 3 - IODC_EN_REM_INVITOM_ALLOCFLOW
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///< 4 - IODC_EN_REM_INVITOM_ALLOC_NONALLOC, 5 - IODC_EN_REM_INVITOM_AND_WCILF
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UINT8 DegradePrecedence; ///< Use DEGRADE_PRECEDENCE definition; TOPOLOGY_PRECEDENCE is default
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UINT8 Degrade4SPreference; ///< 4S1LFullConnect topology is default; another option is 4S2LRing topology.
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UINT8 DirectoryModeEn; ///< 0 - Disable; 1 - Enable (default)
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UINT8 XptPrefetchEn; ///< Xpt Prefetch : 1 - Enable; 0 - Disable; 2 - Auto (default)
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UINT8 KtiPrefetchEn; ///< Kti Prefetch : 1 - Enable; 0 - Disable; 2 - Auto (default)
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UINT8 XptRemotePrefetchEn; ///< Xpt Remote Prefetch : 1 - Enable; 0 - Disable; 2 - Auto (default) (ICX only)
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UINT8 RdCurForXptPrefetchEn; ///< RdCur for XPT Prefetch : 0 - Disable, 1 - Enable, 2- Auto (default)
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UINT8 KtiFpgaEnable[MAX_SOCKET]; ///< Indicate if should enable Fpga device found in this socket : 0 - Disable, 1 - Enable, 2- Auto
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UINT8 DdrtQosMode; ///< DDRT QoS Feature: 0 - Disable (default), 1 - M2M QoS Enable, Cha QoS Disable
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///< 2 - M2M QoS Enable, Cha QoS Enable
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//
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// Phy/Link Layer Options (System-wide and per socket)
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//
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UINT8 KtiLinkSpeedMode; ///< Link speed mode selection; 0 - Slow Speed; 1- Full Speed (default)
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UINT8 KtiLinkSpeed; ///< Use KTI_LINKSPEED definition
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UINT8 KtiAdaptationEn; ///< 0 - Disable, 1 - Enable
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UINT8 KtiAdaptationSpeed; ///< Use KTI_LINK_SPEED definition; MAX_KTI_LINK_SPEED - Auto (i.e BIOS choosen speed)
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UINT8 KtiLinkL0pEn; ///< 0 - Disable, 1 - Enable, 2- Auto (default)
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UINT8 KtiLinkL1En; ///< 0 - Disable, 1 - Enable, 2- Auto (default)
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UINT8 KtiFailoverEn; ///< 0 - Disable, 1 - Enable, 2- Auto (default)
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UINT8 KtiLbEn; ///< 0 - Disable(default), 1 - Enable
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UINT8 KtiCrcMode; ///< CRC_MODE_16BIT, CRC_MODE_ROLLING_32BIT, CRC_MODE_AUTO or CRC_MODE_PER_LINK
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UINT8 KtiCpuSktHotPlugEn; ///< 0 - Disable (default), 1 - Enable
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UINT8 KtiCpuSktHotPlugTopology; ///< 0 - 4S Topology (default), 1 - 8S Topology
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UINT8 KtiSkuMismatchCheck; ///< 0 - No, 1 - Yes (default)
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UINT8 IrqThreshold; ///< IRQ Threshold setting
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UINT8 TorThresLoctoremNorm; ///< TOR threshold - Loctorem threshold normal
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UINT8 TorThresLoctoremEmpty; ///< TOR threshold - Loctorem threshold empty
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UINT8 MbeBwCal; ///< 0 - Linear, 1 - Biased, 2 - Legacy, 3 - AUTO (default = Linear)
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UINT8 TscSyncEn; ///< TSC sync in sockets: 0 - Disable, 1 - Enable, 2 - AUTO (Default)
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UINT8 StaleAtoSOptEn; ///< HA A to S directory optimization: 1 - Enable; 0 - Disable; 2 - Auto (Default)
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UINT8 LLCDeadLineAlloc; ///< LLC dead line alloc: 1 - Enable(Default); 0 - Disable
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UINT8 SplitLock; ///< @deprecated Reserved, must be set to 0.
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UINT8 ColdResetRequestEnd; ///< @deprecated Reserved.
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///
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/// Phy/Link Layer Options (per Port)
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///
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KTI_CPU_SETTING PhyLinkPerPortSetting[MAX_SOCKET];
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UINT8 mmCfgBase; ///< MMCFG Base address, must be 64MB (SKX, HSX, BDX) / 256MB (GROVEPORT) aligned. Options: {0:1G, 1:1.5G, 2:1.75G, 3:2G, 4:2.25G, 5:3G, 6: Auto}
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UINT8 mmCfgSize; ///< MMCFG Size address, must be 64M, 128M or 256M. Options: {0:64M, 1:128M, 2:256M, 3:512M, 4:1G, 5:2G, 6: Auto}
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UINT32 mmiolBase; ///< MMIOL Base address, must be 64MB aligned
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UINT32 mmiolSize; ///< MMIOL Size address
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UINT32 mmiohBase; ///< Address bits above 4GB, i,e, the hex value here is address Bit[45:32] for SKX family, Bit[51:32] for ICX-SP
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UINT8 CpuPaLimit; ///< Limits the max address to 46bits. This will take precedence over mmiohBase
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UINT8 lowGap; ///< @deprecated Reserved.
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UINT8 highGap; ///< @deprecated Reserved.
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UINT16 mmiohSize; ///< Number of 1GB contiguous regions to be assigned for MMIOH space per CPU. Range 1-1024
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UINT8 isocEn; ///< 1 - Enable; 0 - Disable (BIOS will force this for 4S)
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UINT8 dcaEn; ///< 1 - Enable; 0 - Disable
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/**
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BoardTypeBitmask:
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- Bits[3:0] - Socket0
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- Bits[7:4] - Socket1
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- Bits[11:8] - Socket2
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- Bits[15:12] - Socket3
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- Bits[19:16] - Socket4
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- Bits[23:20] - Socket5
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- Bits[27:24] - Socket6
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- Bits[31:28] - Socket7
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Within each Socket-specific field, bits mean:
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- Bit0 = CPU_TYPE_STD support; always 1 on Socket0
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- Bit1 = CPU_TYPE_F support
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- Bit2 = CPU_TYPE_P support
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- Bit3 = reserved
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**/
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UINT32 BoardTypeBitmask;
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UINT32 AllLanesPtr; ///< Pointer to an array of ALL_LANES_EPARAM_LINK_INFO structures.
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UINT32 PerLanePtr; ///< Pointer to an array of PER_LANE_EPARAM_LINK_INFO structures.
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UINT32 AllLanesSizeOfTable; ///< Number of elements in array pointed to by AllLanesPtr
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UINT32 PerLaneSizeOfTable; ///< Number of elements in array pointed to by PerLanePtr
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UINT32 WaitTimeForPSBP; ///< the wait time in units of 1000us for PBSP to check in.
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BOOLEAN IsKtiNvramDataReady; ///< Used internally, Reserved.
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UINT32 OemHookPostTopologyDiscovery; ///< OEM_HOOK_POST_TOPOLOGY_DISCOVERY function pointer. Invoked at the end of topology discovery, used for error reporting.
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UINT32 OemGetResourceMapUpdate; ///< OEM_GET_RESOURCE_MAP_UPDATE function pointer. Allows platform code to adjust the resource map.
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UINT32 OemGetAdaptedEqSettings; ///< @deprecated Reserved, must be set to 0.
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UINT32 OemCheckCpuPartsChangeSwap; ///< @deprecated Reserved, must be set to 0.
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BOOLEAN WaSerializationEn; ///< Enable BIOS serialization WA by PcdWaSerializationEn
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KTI_RESERVED_3 Reserved166;
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KTI_RESERVED_4 Reserved167[MAX_SOCKET];
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UINT8 KtiInEnableMktme; ///< 0 - Disabled; 1 - Enabled; MkTme status decides D2Kti feature state
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/**
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Pointers to the location of the CFR/SINIT binaries.
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Contains a pointer to a 24 byte fixed length array.
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The array contains the 3 instances of the following c-struct
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~~~
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typedef struct {
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UINT32 CfrImagePtr;
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UINT32 CfrImageSize;
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}
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~~~
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This allows a maximum of 3 CFR/SINIT binaries to be provided by platform code.
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**/
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UINT32 CFRImagePtr;
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UINT8 S3mCFRCommit; ///< 0 - Disable S3m CFR flow. 1 - Provision S3m CFR but not Commit. 2 - Provision and Commit S3M CFR.
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UINT8 PucodeCFRCommit; ///< 0 - Disable Pucode CFR flow. 1 - Provision Pucode CFR but not Commit. 2 - Provision and Commit Pucode CFR.
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} KTI_HOST_IN;
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#pragma pack()
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#endif // _KTI_HOST_H_
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