/** @file
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System Infor Var Hearder File
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@copyright
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Copyright 2017 - 2021 Intel Corporation. <BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef __SYSTEM_INFO_VAR_INCLUDES__
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#define __SYSTEM_INFO_VAR_INCLUDES__
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#include <MemCommon.h>
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#include <Upi/KtiSi.h>
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#include <Pi/PiBootMode.h>
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#define SYS_INFO_NVRAM_VAR_NAME L"InfoVarNvramData"
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#pragma pack (push,1)
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typedef enum BootMode {
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NormalBoot = 0, // Normal path through RC with full init, mem detection, init, training, etc.
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// Some of these MRC specific init routines can be skipped based on MRC input params
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// in addition to the sub-boot type (WarmBoot, WarmBootFast, etc).
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S3Resume = 1 // S3 flow through RC. Should do the bare minimum required for S3
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// init and be optimized for speed.
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} BootMode;
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//
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// This is used to determine what type of die is connected to a UPI link
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//
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typedef enum {
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UpiConnectionTypeCpu,
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UpiConnectionTypePcieGen4,
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UpiConnectionTypeFpga,
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UpiConnectionTypeMax
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} UPI_CONNECTION_TYPE;
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typedef struct {
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UINT16 stackPresentBitmap[MAX_SOCKET]; ///< bitmap of present stacks per socket
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UINT8 StackBus[MAX_SOCKET][MAX_LOGIC_IIO_STACK];///< Bus of each stack
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UINT32 StackMmiol[MAX_SOCKET][MAX_IIO_STACK]; ///< mmiol of each IIO stack, if it works as CXL, the mmiol base is RCRBBAR
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UINT8 SocketFirstBus[MAX_SOCKET];
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UINT8 Socket10nmUboxBus0[MAX_SOCKET]; //10nm CPU use only
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UINT8 SocketLastBus[MAX_SOCKET];
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UINT8 segmentSocket[MAX_SOCKET];
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UINT8 KtiPortCnt;
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UINT32 socketPresentBitMap;
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UINT32 SecondaryDieBitMap;
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UINT32 FpgaPresentBitMap;
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UINT32 mmCfgBase;
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UINT32 mmCfgBaseH[MAX_SOCKET];
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UINT32 mmCfgBaseL[MAX_SOCKET];
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UINT8 DdrMaxCh;
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UINT8 DdrMaxImc;
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UINT8 DdrNumChPerMc;
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UINT8 imcEnabled[MAX_SOCKET][MAX_IMC];
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UINT8 mcId[MAX_SOCKET][MAX_CH];
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MRC_MST MemSsType[MAX_SOCKET];
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UINT32 MmioBar[MAX_SOCKET][TYPE_MAX_MMIO_BAR];
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UINT8 HbmMaxCh;
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UINT8 HbmMaxIoInst;
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UINT8 HbmNumChPerMc;
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UINT8 HbmNumChPerIo;
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UINT32 LastCsrAddress[2];
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UINT32 LastCsrMmioAddr;
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UINT8 CsrCachingEnable;
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UINT32 LastCsrMcAddress[2];
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UINT32 LastCsrMcMmioPhyAddr;
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UINT8 CsrPciBarCachingEnable;
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UINT32 LastCsrPciBarAddr[2];
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UINT64 LastCsrPciBarPhyAddr;
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UINT32 LastSBPortId[MAX_SOCKET];
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UPI_CONNECTION_TYPE UpiConnectionType[MAX_SOCKET];
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BOOLEAN PostedCsrAccessAllowed; // SW is allowed to use posted CSR writes method when TRUE
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BOOLEAN PostedWritesEnabled; // All CSR writes use posted method when TRUE, non-posted when FALSE
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BOOLEAN DataPopulated; // CPU_CSR_ACCESS_VAR is unavailable when FALSE
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BOOLEAN HbmSku;
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UINT8 SocketConfig;
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UINT8 HcxType[MAX_SOCKET];
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} CPU_CSR_ACCESS_VAR;
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typedef struct {
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UINT32 MeRequestedSizeNv;
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UINT32 MeRequestedAlignmentNv;
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UINT32 IeRequestedSizeNv;
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UINT32 IeRequestedAlignmentNv;
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UINT8 SbspSocketIdNv;
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} SYS_INFO_VAR_NVRAM;
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#pragma pack (pop)
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#endif //#ifndef __SYSTEM_INFO_VAR_INCLUDES__
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