/** @file
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Definition of the global NVS area protocol. This protocol
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publishes the address and format of a global ACPI NVS buffer used as a communications
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buffer between SMM code and ASL code.
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Note: Data structures defined in this protocol are not naturally aligned.
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@copyright
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Copyright 2004 - 2021 Intel Corporation. <BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef _EFI_GLOBAL_NVS_AREA_H_
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#define _EFI_GLOBAL_NVS_AREA_H_
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//
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// Global NVS Area Protocol GUID
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//
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#define EFI_GLOBAL_NVS_AREA_PROTOCOL_GUID { 0x74e1e48, 0x8132, 0x47a1, 0x8c, 0x2c, 0x3f, 0x14, 0xad, 0x9a, 0x66, 0xdc }
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//
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// Because of ASL constrains cannot use MAX_SOCKET and MAX_LOGIC_IIO_STACK to configure ACPI objects. The symbols
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// below are the largest values of MAX_SOCKET or MAX_LOGIC_IIO_STACK currently supported in BiosParameterRegion.asi.
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//
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#define NVS_MAX_SOCKETS 8
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#define NVS_MAX_LOGIC_IIO_STACKS 14
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#if NVS_MAX_SOCKETS < MAX_SOCKET
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#error "Must update NVS_MAX_SOCKETS and BiosParameterRegion.asi to handle so many sockets"
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#endif
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#if NVS_MAX_LOGIC_IIO_STACKS < MAX_LOGIC_IIO_STACK
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#error "Must update NVS_MAX_LOGIC_IIO_STACKS and BiosParameterRegion.asi to handle so many stacks"
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#endif
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//
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// Extern the GUID for protocol users.
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//
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extern EFI_GUID gEfiGlobalNvsAreaProtocolGuid;
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//
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// Global NVS Area definition
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// BIOS parameters region provided by POST code to ASL, defined as PSYS in BiosParametersRegion.asi
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//
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#pragma pack (1)
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typedef struct {
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// IOAPIC Start
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UINT32 PlatformId;
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UINT64 IoApicEnable;
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UINT8 ApicIdOverrided :1;
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UINT8 PchIoApic_24_119 :1;
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UINT8 Cpx4Detect :1;
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UINT8 Reserved0 :5;
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// IOAPIC End
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// Power Management Start
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UINT8 TpmEnable :1;
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UINT8 CStateEnable :1;
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UINT8 C3Enable :1;
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UINT8 C6Enable :1;
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UINT8 C7Enable :1;
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UINT8 MonitorMwaitEnable :1;
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UINT8 PStateEnable :1;
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UINT8 EmcaEn :1;
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UINT8 HWAllEnable :2;
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UINT8 KBPresent :1;
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UINT8 MousePresent :1;
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UINT8 TStateEnable :1;
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UINT8 TStateFineGrained :1;
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UINT8 OSCX :1;
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UINT8 Reserved1 :1;
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// Power Management End
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// RAS Start
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UINT8 CpuChangeMask;
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UINT8 IioChangeMask;
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UINT16 IioPresentBitMask[NVS_MAX_SOCKETS];
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UINT32 SocketBitMask; // make sure this is at 4byte boundary
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UINT8 CpuCoreThreadsCount;
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UINT32 ProcessorApicIdBase[NVS_MAX_SOCKETS];
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UINT64 ProcessorBitMask[NVS_MAX_SOCKETS]; // cores 0-63 for each socket
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UINT64 ProcessorBitMaskHi[NVS_MAX_SOCKETS]; // cores 64-127 for each socket
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UINT32 MmCfg;
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UINT32 TsegSize;
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UINT32 SmiRequestParam[4];
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UINT32 SciRequestParam[4];
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UINT64 MigrationActionRegionAddress;
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UINT8 Cpu0Uuid[16];
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UINT8 Cpu1Uuid[16];
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UINT8 Cpu2Uuid[16];
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UINT8 Cpu3Uuid[16];
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UINT8 Cpu4Uuid[16];
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UINT8 Cpu5Uuid[16];
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UINT8 Cpu6Uuid[16];
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UINT8 Cpu7Uuid[16];
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UINT8 CpuSpareMask;
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UINT8 Mem0Uuid[16];
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UINT8 Mem1Uuid[16];
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UINT8 Mem2Uuid[16];
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UINT8 Mem3Uuid[16];
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UINT8 Mem4Uuid[16];
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UINT8 Mem5Uuid[16];
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UINT8 Mem6Uuid[16];
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UINT8 Mem7Uuid[16];
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UINT8 Mem8Uuid[16];
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UINT8 Mem9Uuid[16];
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UINT8 Mem10Uuid[16];
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UINT8 Mem11Uuid[16];
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UINT8 Mem12Uuid[16];
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UINT8 Mem13Uuid[16];
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UINT8 Mem14Uuid[16];
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UINT8 Mem15Uuid[16];
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UINT64 EmcaL1DirAddr;
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UINT32 ProcessorId;
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UINT8 PcieAcpiHotPlugEnable;
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UINT8 WheaEnabled;
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UINT8 WheaSci;
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UINT8 PropagateSerrOption;
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UINT8 PropagatePerrOption;
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// RAS End
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// VTD Start
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UINT64 DrhdAddr[3];
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UINT64 AtsrAddr[3];
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UINT64 RhsaAddr[3];
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// VTD End
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// SR-IOV WA Start
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UINT8 WmaaSICaseValue;
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UINT16 WmaaSISeg;
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UINT8 WmaaSIBus;
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UINT8 WmaaSIDevice;
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UINT8 WmaaSIFunction;
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UINT8 WmaaSISts;
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UINT8 WheaSupportEn;
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// SR-IOV End
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// BIOS Guard Start
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UINT64 BiosGuardMemAddress;
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UINT8 BiosGuardMemSize;
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UINT16 BiosGuardIoTrapAddress;
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UINT8 CpuSkuNumOfBitShift;
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// BIOS Guard End
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// USB3 Start
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UINT8 XhciMode;
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UINT8 HostAlertVector1;
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UINT8 HostAlertVector2;
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// USB3 End
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// HWPM Start
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UINT8 HWPMEnable :2; // HWPM
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UINT8 Reserved3 :1; // reserved bit
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UINT8 HwpInterrupt :1; // HWP Interrupt
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UINT8 Reserved2 :4; // reserved bits
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// HWPM End
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// SGX Start
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UINT8 SgxStatus;
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UINT64 EpcLength[8]; // MAX_IMC * MAX_SOCKET
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UINT64 EpcBaseAddress[8]; // MAX_IMC * MAX_SOCKET
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// SGX End
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// PCIe Multi-Seg Start
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UINT8 BusBase[NVS_MAX_SOCKETS][NVS_MAX_LOGIC_IIO_STACKS]; // PCI bus base number for each stack
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UINT8 PcieMultiSegSupport; // Enable /Disable switch
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UINT8 PcieSegNum[NVS_MAX_SOCKETS]; // PCI segment number array for each socket
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// PCIe Multi-seg end
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UINT8 SncAnd2Cluster; // 0 - SNC disabled, 2 - SNC enabled (2 clusters), 4 - SNC enabled (4 clusters)
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// XTU Start
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UINT32 XTUBaseAddress; // 193 XTU Base Address
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UINT32 XTUSize; // 197 XTU Entries Size
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UINT32 XMPBaseAddress; // 201 XTU Base Address
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UINT8 DDRReferenceFreq; // 205 DDR Reference Frequency
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UINT8 Rtd3Support; // 206 Runtime D3 support.
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UINT8 Rtd3P0dl; // 207 User selctable Delay for Device D0 transition.
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UINT8 Rtd3P3dl; // 208 User selctable Delay for Device D0 transition.
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// XTU End
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// FPGA Root Port Bus
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UINT8 FpgaBusBase[8];
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UINT8 FpgaBusLimit[8];
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// FPGA present bit
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UINT8 FpgaPresent[8];
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// FPGA Resource Allocation
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UINT32 VFPBMemBase[8];
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UINT32 VFPBMemLimit[8];
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// FPGA KTI present bitmap
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UINT32 FpgaKtiPresent;
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// FPGA Bus for KTI
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UINT8 FpgaKtiBase[8];
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UINT16 PmBase; // ACPI IO Base Address
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UINT8 DebugModeIndicator; // Debug Mode Indicator
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UINT8 IioPcieRpCapOffset; // IIO PCIe root port PCIe Capability offset
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UINT8 ArtTscLinkFlag; // Flag to indicate if TSC is linked to ART
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} BIOS_ACPI_PARAM;
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#pragma pack ()
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//
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// Global NVS Area Protocol
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//
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typedef struct _EFI_GLOBAL_NVS_AREA_PROTOCOL {
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BIOS_ACPI_PARAM *Area;
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} EFI_GLOBAL_NVS_AREA_PROTOCOL;
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#endif
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