/** @file
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UBS silicon access PPI
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This PPI abstracts all UBA silicon accesses
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@copyright
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Copyright 2021 Intel Corporation. <BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef _DYNAMIC_SI_LIBARY_PPI_H_
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#define _DYNAMIC_SI_LIBARY_PPI_H_
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// {C1176733-159F-42d5-BCB9-320660B17310}
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#define DYNAMIC_SI_LIBARY_PPI_GUID \
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{ 0x4e18e22b, 0x5034, 0x4512, { 0xb7, 0xe5, 0x0b, 0xf1, 0x9d, 0xe3, 0x59, 0x8c } }
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#define UBA_ACCESS_PPI_VERSION 01
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#define UBA_ACCESS_PPI_SIGNATURE SIGNATURE_32('D', 'S', 'L', 'P')
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#include <Library/SpsPeiLib.h>
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#include <IioPlatformData.h>
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#include <GpioConfig.h>
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#include <Library/PchInfoLib.h>
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#include <Library/GpioLib.h>
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//
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// Functions
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//
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typedef
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EFI_STATUS
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(EFIAPI *PEI_GET_GPIO_INPUT_VALUE) (
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IN GPIO_PAD GpioPad,
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OUT UINT32 *InputVal
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);
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typedef
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EFI_STATUS
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(EFIAPI *PEI_SET_GPIO_OUTPUT_VALUE) (
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IN GPIO_PAD GpioPad,
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IN UINT32 Value
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);
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typedef
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EFI_STATUS
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(EFIAPI *PEI_GPIO_SET_PAD) (
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IN GPIO_PAD GpioPad,
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IN GPIO_CONFIG *GpioData
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);
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typedef
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UINT16
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(EFIAPI *PEI_GET_PCH_DEVICE_ID) (
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VOID
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);
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typedef
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PCH_SERIES
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(EFIAPI *PEI_GET_PCH_SERIES) (
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VOID
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);
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typedef
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PCH_STEPPING
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(EFIAPI *PEI_GET_PCH_STEPPING) (
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VOID
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);
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typedef
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BOOLEAN
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(EFIAPI *PEI_IS_PCH_GBE_REGION_VALID) (
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VOID
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);
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typedef
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UINT32
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(EFIAPI *PEI_GET_PCH_GBE_PORT_NUMBER) (
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VOID
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);
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typedef
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BOOLEAN
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(EFIAPI *PEI_IS_PCH_GBE_PRESENT) (
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VOID
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);
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typedef
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VOID
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(EFIAPI *PEI_PchDisableGbe) (
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VOID
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);
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typedef
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VOID
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(EFIAPI *PEI_PchDisableGbeByPchId) (
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IN UINT8 PchId
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);
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typedef
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EFI_STATUS
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(EFIAPI *PEI_GpioConfigurePadsByPchId) (
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IN UINT8 PchId,
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IN UINT32 NumberOfItems,
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IN GPIO_INIT_CONFIG *GpioInitTableAddress
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);
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typedef
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EFI_STATUS
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(EFIAPI *PEI_GpioGetInputValueByPchId) (
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IN UINT8 PchId,
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IN GPIO_PAD GpioPad,
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OUT UINT32 *InputVal
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);
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typedef
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EFI_STATUS
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(EFIAPI *PEI_PeiGetCurrenClockingMode) (
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OUT CLOCKING_MODES *ClockingMode
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);
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typedef
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EFI_STATUS
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(EFIAPI *PEI_GetPchPcieRpDevFunByPchId) (
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IN UINT8 PchId,
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IN UINTN RpNumber,
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OUT UINTN *RpDev,
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OUT UINTN *RpFun
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);
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typedef
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BOOLEAN
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(EFIAPI *PEI_IsSimicsEnvironment) (
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VOID
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);
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typedef
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UINT8
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(EFIAPI *PEI_GetPchMaxSataPortNum) (
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VOID
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);
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typedef
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UINT8
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(EFIAPI *PEI_GetPchMaxsSataPortNum) (
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VOID
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);
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typedef
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EFI_STATUS
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(EFIAPI *PEI_GpioSetPadConfigByPchId) (
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IN UINT8 PchId,
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IN GPIO_PAD GpioPad,
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IN GPIO_CONFIG *GpioData
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);
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typedef
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UINT8
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(EFIAPI *PEI_GetPchMaxPciePortNum) (
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VOID
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);
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typedef
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EFI_STATUS
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(EFIAPI *PEI_PchGetSataLaneNumByPchId) (
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IN UINT8 PchId,
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UINT32 SataLaneIndex,
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UINT8 *LaneNum
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);
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typedef
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EFI_STATUS
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(EFIAPI *PEI_PchGetPcieLaneNumByPchId) (
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IN UINT8 PchId,
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UINT32 PcieLaneIndex,
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UINT8 *LaneNum
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);
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typedef
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EFI_STATUS
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(EFIAPI *PEI_PchGetsSataLaneNumByPchId) (
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IN UINT8 PchId,
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UINT32 SataLaneIndex,
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UINT8 *LaneNum
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);
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typedef
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UINTN
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(EFIAPI *PEI_MmPciBase) (
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IN UINT32 Bus,
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IN UINT32 Device,
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IN UINT32 Function
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);
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typedef
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BOOLEAN
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(EFIAPI *PEI_HybridSystemLevelEmulationEnabled) (
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VOID
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);
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typedef
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BOOLEAN
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(EFIAPI *PEI_IioIsSocketPresent) (
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IN UINT8 IioIndex
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);
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typedef
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UINT8
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(EFIAPI *PEI_GetMaxPortNumPerSocket) (
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VOID
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);
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typedef
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BOOLEAN
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(EFIAPI *PEI_IsVMDEnabledForPort) (
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IN UINT8 IioIndex,
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IN UINT8 PortIndex
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);
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typedef
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BOOLEAN
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(EFIAPI *PEI_IioAreLanesAssignedToPort) (
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IN IIO_GLOBALS *IioGlobalData,
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IN UINT8 IioIndex,
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IN UINT8 PortIndex
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);
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typedef
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UINT8
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(EFIAPI *PEI_GetPortIndexbyStack) (
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IN UINT8 StackIndex,
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IN UINT8 PortIndex
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);
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typedef
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BOOLEAN
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(EFIAPI *PEI_IsDmiStack) (
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IN UINT8 Stack
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);
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typedef
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BOOLEAN
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(EFIAPI *PEI_IsCpuAndRevision) (
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IN UINT8 CpuType,
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IN UINT16 Revision
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);
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typedef
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UINT8
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(EFIAPI *PEI_GetMaxStackNumPerSocket) (
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VOID
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);
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typedef
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BOOLEAN
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(EFIAPI *PEI_IioIsStackPresent) (
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IN UINT8 IioIndex,
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IN UINT8 StackIndex
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);
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typedef
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UINT8
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(EFIAPI *PEI_GetMaxPortNumPerStack) (
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IN UINT8 Stack
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);
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//
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// From KtiApi.h
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//
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typedef
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BOOLEAN
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(EFIAPI *PEI_SocketPresent) (
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IN UINT32 SocId
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);
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/**
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Get SVID Mapping from Socket and MCID
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@param[in] Socket - Socket Id - 0 based
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@param[in] McId - Memory controller 0 based
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@param[in] SvidValue - SVID Value
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@retval EFI_SUCCESS - Value found
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@retval EFI_NOT_FOUND - Value not found
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**/
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typedef
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EFI_STATUS
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(EFIAPI *PEI_GetSvidMap) (
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IN UINT8 Socket,
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IN UINT8 McId,
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IN UINT8 *SvidValue
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);
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typedef
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UINT16
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(EFIAPI *PEI_PmcGetAcpiBase) (
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VOID
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);
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typedef
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UINT16
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(EFIAPI *PEI_PmcGetAcpiBaseByPchId) (
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IN UINT8 PchId
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);
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typedef
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EFI_STATUS
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(EFIAPI *PEI_PchLpcIoDecodeRangesSet) (
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IN UINT16 LpcIoDecodeRanges
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);
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typedef
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VOID
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(EFIAPI *PEI_CheckPowerOffNow) (
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VOID
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);
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typedef
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VOID
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(EFIAPI *PEI_PmcSetPlatformStateAfterPowerFailure) (
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IN UINT8 PowerStateAfterG3
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);
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typedef
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VOID
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(EFIAPI *PEI_PmcClearPowerFailureStatus) (
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VOID
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);
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typedef
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BOOLEAN
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(EFIAPI *PEI_PmcIsPowerFailureDetected) (
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VOID
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);
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typedef
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EFI_STATUS
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(EFIAPI *PEI_PchLpcGenIoRangeSet) (
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IN UINT16 Address,
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IN UINTN Length
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);
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typedef
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EFI_STATUS
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(EFIAPI *PEI_PchLpcIoEnableDecodingSet) (
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IN UINT16 LpcIoEnableDecoding
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);
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typedef
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EFI_STATUS
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(EFIAPI *PEI_PchPcrAndThenOr32) (
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IN PCH_SBI_PID Pid,
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IN UINT16 Offset,
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IN UINT32 AndData,
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IN UINT32 OrData
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);
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typedef
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EFI_STATUS
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(EFIAPI *PEI_PchPcrRead32ByPchId) (
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IN UINT8 PchId,
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IN PCH_SBI_PID Pid,
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IN UINT16 Offset,
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OUT UINT32 *OutData
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);
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typedef
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UINT8
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(EFIAPI *PEI_ReadNmiEn) (
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VOID
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);
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typedef
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UINT8
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(EFIAPI *PEI_GetPchXhciMaxUsb2PortNum) (
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VOID
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);
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typedef
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UINT8
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(EFIAPI *PEI_GetPchXhciMaxUsb3PortNum) (
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VOID
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);
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typedef
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BOOLEAN
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(EFIAPI *PEI_PchIsGbeAvailable) (
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VOID
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);
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typedef
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EFI_STATUS
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(EFIAPI *PEI_EnableMcaOnCacheableMmio) (
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VOID
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);
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typedef
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BOOLEAN
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(EFIAPI *PEI_X2ApicIdDetect) (
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IN VOID *Host
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);
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//
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// Abstracting silicon functional implementations from OpenBoardPkg code
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//
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typedef struct {
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UINT32 Signature;
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UINT32 Version;
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PEI_GET_GPIO_INPUT_VALUE GpioGetInputValue;
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PEI_SET_GPIO_OUTPUT_VALUE GpioSetOutputValue;
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PEI_GPIO_SET_PAD GpioSetPadConfig;
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PEI_GET_PCH_DEVICE_ID GetPchLpcDeviceId;
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PEI_GET_PCH_SERIES GetPchSeries;
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PEI_GET_PCH_STEPPING PchStepping;
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PEI_IS_PCH_GBE_REGION_VALID PchIsGbeRegionValid;
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PEI_GET_PCH_GBE_PORT_NUMBER PchGetGbePortNumber;
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PEI_IS_PCH_GBE_PRESENT PchIsGbePresent;
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PEI_PchDisableGbeByPchId PchDisableGbeByPchId;
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PEI_GpioConfigurePadsByPchId GpioConfigurePadsByPchId;
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PEI_GpioSetPadConfigByPchId GpioSetPadConfigByPchId;
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PEI_GpioGetInputValueByPchId GpioGetInputValueByPchId;
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PEI_PeiGetCurrenClockingMode PeiGetCurrenClockingMode;
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PEI_GetPchPcieRpDevFunByPchId GetPchPcieRpDevFunByPchId;
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PEI_IsSimicsEnvironment IsSimicsEnvironment;
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PEI_GetPchMaxSataPortNum GetPchMaxSataPortNum;
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PEI_GetPchMaxsSataPortNum GetPchMaxsSataPortNum;
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PEI_GetPchMaxPciePortNum GetPchMaxPciePortNum;
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PEI_PchGetSataLaneNumByPchId PchGetSataLaneNumByPchId;
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PEI_PchGetsSataLaneNumByPchId PchGetsSataLaneNumByPchId;
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PEI_PchGetPcieLaneNumByPchId PchGetPcieLaneNumByPchId;
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PEI_MmPciBase MmPciBase;
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PEI_HybridSystemLevelEmulationEnabled HybridSystemLevelEmulationEnabled;
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PEI_IioIsSocketPresent IioIsSocketPresent;
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PEI_GetMaxPortNumPerSocket GetMaxPortNumPerSocket;
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PEI_IsVMDEnabledForPort IsVMDEnabledForPort;
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PEI_IioAreLanesAssignedToPort IioAreLanesAssignedToPort;
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PEI_GetPortIndexbyStack GetPortIndexbyStack;
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PEI_IsDmiStack IsDmiStack;
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PEI_IsCpuAndRevision IsCpuAndRevision;
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PEI_PchDisableGbe PchDisableGbe;
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PEI_GetMaxStackNumPerSocket GetMaxStackNumPerSocket;
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PEI_IioIsStackPresent IioIsStackPresent;
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PEI_GetMaxPortNumPerStack GetMaxPortNumPerStack;
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PEI_SocketPresent SocketPresent;
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PEI_GetSvidMap GetSvidMap;
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PEI_PmcGetAcpiBase PmcGetAcpiBase;
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PEI_PmcGetAcpiBaseByPchId PmcGetAcpiBaseByPchId;
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PEI_PchLpcIoDecodeRangesSet PchLpcIoDecodeRangesSet;
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PEI_CheckPowerOffNow CheckPowerOffNow;
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PEI_PmcSetPlatformStateAfterPowerFailure PmcSetPlatformStateAfterPowerFailure;
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PEI_PmcClearPowerFailureStatus PmcClearPowerFailureStatus;
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PEI_PmcIsPowerFailureDetected PmcIsPowerFailureDetected;
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PEI_PchLpcGenIoRangeSet PchLpcGenIoRangeSet;
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PEI_PchLpcIoEnableDecodingSet PchLpcIoEnableDecodingSet;
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PEI_PchPcrAndThenOr32 PchPcrAndThenOr32;
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PEI_PchPcrRead32ByPchId PchPcrRead32ByPchId;
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PEI_ReadNmiEn ReadNmiEn;
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PEI_GetPchXhciMaxUsb2PortNum GetPchXhciMaxUsb2PortNum;
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PEI_GetPchXhciMaxUsb3PortNum GetPchXhciMaxUsb3PortNum;
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PEI_PchIsGbeAvailable PchIsGbeAvailable;
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PEI_EnableMcaOnCacheableMmio EnableMcaOnCacheableMmio;
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PEI_X2ApicIdDetect X2ApicIdDetect;
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} DYNAMIC_SI_LIBARY_PPI;
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extern EFI_GUID gDynamicSiLibraryPpiGuid;
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#endif // _DYNAMIC_SI_LIBARY_PPI_H_
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